An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1μm DRAM

Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    39 Citations (Scopus)

    Abstract

    This paper presents an 8Tb/s 1pJ/b 0.8mm2/Tb/s quad data rate (QDR) inductive-coupling interface between 65nm CMOS GPU and 0.1μ m DRAM. The interface consists of 1024-bit parallel inductive-coupling transceivers operating at 8Gb/s/link. In the DRAM transceiver, data are multiplexed and demultiplexed by using a quadrature clock and XOR operation. This circuit technique for QDR compensates for transistor performance gap between the GPU and the DRAM to achieve 8Gb/s bandwidth. The clock for data retiming is recovered from the received data by using an injection-lock VCO. Clock links and clock distribution circuits are not needed, resulting in small layout area of 0.8mm2/Tb/s. Frontend of the transceiver is implemented using NMOS CML circuits with adaptive bias control. The transceiver's sensitivity to PVT variations is small, enabling all the 1024 parallel transceivers to operate at BER<10-16. It also reduces the design margin required of the transceiver, resulting in power reduction to 1pJ/b. Compared to the latest wired 40nm DRAM interface [1], the bandwidth is 32x higher, while the energy consumption is 1/8 and the layout area is 1/22.

    Original languageEnglish
    Title of host publication2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
    Pages436-437
    Number of pages2
    DOIs
    Publication statusPublished - 2010 May 18
    Event2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States
    Duration: 2010 Feb 72010 Feb 11

    Publication series

    NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    Volume53
    ISSN (Print)0193-6530

    Other

    Other2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
    CountryUnited States
    CitySan Francisco, CA
    Period10/2/710/2/11

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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  • Cite this

    Miura, N., Kasuga, K., Saito, M., & Kuroda, T. (2010). An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1μm DRAM. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers (pp. 436-437). [5433909] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 53). https://doi.org/10.1109/ISSCC.2010.5433909