An adaptive DAC settling waiting time optimized ultra low voltage asynchronous SAR ADC in 40 nm CMOS

Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    An ultra low power and low voltage successive-approximation-register (SAR) analog-to-digital converter (ADC) with timing optimized asynchronous clock generator is presented. By calibrating the delay amount of the clock generator, the DAC settling waiting time is adaptively optimized to counter the device mismatch. This technique improved the maximum sampling frequency by 40% keeping ENOB around 7-bit at 0.4 V analog and 0.7 V digital power supply voltage. The delay time dependency on power supply has small effect to the accuracy of conversion. Decreasing of supply voltage by 9% degrades ENOB only by 0.1-bit, and the proposed calibration can give delay margins for high voltage swing. The prototype ADC fabricated in 40 nm CMOS process achieved figure of merit (FoM) of 8.75-fJ/conversion-step with 2.048 MS/s at 0.6 V analog and 0.7 V digital power supply voltage. The ADC can operates from 50 S/s to 8 MS/s keeping ENOB over 7.5-bit.

    Original languageEnglish
    Pages (from-to)820-827
    Number of pages8
    JournalIEICE Transactions on Electronics
    VolumeE96-C
    Issue number6
    DOIs
    Publication statusPublished - 2013 Jun

    Keywords

    • ADC
    • Asynchronous
    • SAR
    • Ultra low power

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

    Fingerprint Dive into the research topics of 'An adaptive DAC settling waiting time optimized ultra low voltage asynchronous SAR ADC in 40 nm CMOS'. Together they form a unique fingerprint.

  • Cite this