An adaptive Viterbi decoder on the dynamically reconfigurable processor

Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics' DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the Signal to Noise Ratio. The power can be saved up to 58.3% and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long.

Original languageEnglish
Title of host publicationProceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006
Pages285-288
Number of pages4
DOIs
Publication statusPublished - 2006
Event2006 IEEE International Conference on Field Programmable Technology, FPT 2006 - Bangkok, Thailand
Duration: 2006 Dec 132006 Dec 15

Other

Other2006 IEEE International Conference on Field Programmable Technology, FPT 2006
CountryThailand
CityBangkok
Period06/12/1306/12/15

Fingerprint

Throughput
Base stations
Signal to noise ratio
Electric power utilization
Electronic equipment

ASJC Scopus subject areas

  • Software

Cite this

Abe, S., Hasegawa, Y., Toi, T., Inuo, T., & Amano, H. (2006). An adaptive Viterbi decoder on the dynamically reconfigurable processor. In Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006 (pp. 285-288). [4042451] https://doi.org/10.1109/FPT.2006.270329

An adaptive Viterbi decoder on the dynamically reconfigurable processor. / Abe, Shohei; Hasegawa, Yohei; Toi, Takao; Inuo, Takeshi; Amano, Hideharu.

Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006. 2006. p. 285-288 4042451.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abe, S, Hasegawa, Y, Toi, T, Inuo, T & Amano, H 2006, An adaptive Viterbi decoder on the dynamically reconfigurable processor. in Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006., 4042451, pp. 285-288, 2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, 06/12/13. https://doi.org/10.1109/FPT.2006.270329
Abe S, Hasegawa Y, Toi T, Inuo T, Amano H. An adaptive Viterbi decoder on the dynamically reconfigurable processor. In Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006. 2006. p. 285-288. 4042451 https://doi.org/10.1109/FPT.2006.270329
Abe, Shohei ; Hasegawa, Yohei ; Toi, Takao ; Inuo, Takeshi ; Amano, Hideharu. / An adaptive Viterbi decoder on the dynamically reconfigurable processor. Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006. 2006. pp. 285-288
@inproceedings{6ab11068e767498988c94ae2630c07f9,
title = "An adaptive Viterbi decoder on the dynamically reconfigurable processor",
abstract = "In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics' DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the Signal to Noise Ratio. The power can be saved up to 58.3{\%} and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long.",
author = "Shohei Abe and Yohei Hasegawa and Takao Toi and Takeshi Inuo and Hideharu Amano",
year = "2006",
doi = "10.1109/FPT.2006.270329",
language = "English",
isbn = "0780397282",
pages = "285--288",
booktitle = "Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006",

}

TY - GEN

T1 - An adaptive Viterbi decoder on the dynamically reconfigurable processor

AU - Abe, Shohei

AU - Hasegawa, Yohei

AU - Toi, Takao

AU - Inuo, Takeshi

AU - Amano, Hideharu

PY - 2006

Y1 - 2006

N2 - In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics' DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the Signal to Noise Ratio. The power can be saved up to 58.3% and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long.

AB - In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics' DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the Signal to Noise Ratio. The power can be saved up to 58.3% and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long.

UR - http://www.scopus.com/inward/record.url?scp=43749098319&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=43749098319&partnerID=8YFLogxK

U2 - 10.1109/FPT.2006.270329

DO - 10.1109/FPT.2006.270329

M3 - Conference contribution

AN - SCOPUS:43749098319

SN - 0780397282

SN - 9780780397286

SP - 285

EP - 288

BT - Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

ER -