TY - GEN
T1 - An adaptive Viterbi decoder on the dynamically reconfigurable processor
AU - Abe, Shohei
AU - Hasegawa, Yohei
AU - Toi, Takao
AU - Inuo, Takeshi
AU - Amano, Hideharu
PY - 2006
Y1 - 2006
N2 - In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics' DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the Signal to Noise Ratio. The power can be saved up to 58.3% and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long.
AB - In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics' DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the Signal to Noise Ratio. The power can be saved up to 58.3% and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long.
UR - http://www.scopus.com/inward/record.url?scp=43749098319&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=43749098319&partnerID=8YFLogxK
U2 - 10.1109/FPT.2006.270329
DO - 10.1109/FPT.2006.270329
M3 - Conference contribution
AN - SCOPUS:43749098319
SN - 0780397282
SN - 9780780397286
T3 - Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006
SP - 285
EP - 288
BT - Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006
T2 - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006
Y2 - 13 December 2006 through 15 December 2006
ER -