An adaptive Viterbi decoder on the dynamically reconfigurable processor

Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics' DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the Signal to Noise Ratio. The power can be saved up to 58.3% and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long.

Original languageEnglish
Title of host publicationProceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006
Pages285-288
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
Event2006 IEEE International Conference on Field Programmable Technology, FPT 2006 - Bangkok, Thailand
Duration: 2006 Dec 132006 Dec 15

Publication series

NameProceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

Other

Other2006 IEEE International Conference on Field Programmable Technology, FPT 2006
CountryThailand
CityBangkok
Period06/12/1306/12/15

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ASJC Scopus subject areas

  • Software

Cite this

Abe, S., Hasegawa, Y., Toi, T., Inuo, T., & Amano, H. (2006). An adaptive Viterbi decoder on the dynamically reconfigurable processor. In Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006 (pp. 285-288). [4042451] (Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006). https://doi.org/10.1109/FPT.2006.270329