An analytical network performance model for SIMD processor CSX600 interconnects

Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano

Research output: Contribution to journalArticlepeer-review

Abstract

One of the essential factors for an efficiently implementing and tuning applications on an SIMD many-core processor is to become familiar with the schematics of its networks-on-chip (NoC) architecture and performance. This paper focuses on modeling end-to-end latency of a one-dimensional SIMD many-core processor. In order to study precise and practical characteristics of actual end-to-end latency of modern SIMD many-core processors, this work analyzes performance of Swazzle and ClearConnect, both of which are one-dimensional NoCs of ClearSpeed's CSX600, an SIMD processor consisting of 96 Processing Elements (PEs). Evaluation and analysis results have shown that (1) the number of used PEs, (2) the size of transferred data, and (3) data alignment of a shared memory are dominant factors of network performance of CSX600. Based on these observations, we built a model for computing communication time. Using the model, we estimated the best- and the worst-case latencies for traffic patterns taken from several parallel application benchmarks. Finally, we confirmed that actual communication time of the benchmarks fit in between the best- and the worst-case values.

Original languageEnglish
Pages (from-to)146-159
Number of pages14
JournalJournal of Systems Architecture
Volume57
Issue number1
DOIs
Publication statusPublished - 2011 Jan 1

Keywords

  • Many-core processor
  • Network-on-chips (NoCs)
  • SIMD

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture

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