An efficient and scalable implementation of sliding-window aggregate operator on FPGA

Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents an efficient and scalable implementation of an FPGA-based accelerator for sliding-window aggregates over disordered data streams. With an increasing number of overlapping sliding-windows, the window aggregates have a serious scalability issue, especially when it comes to implementing them in parallel processing hardware (e.g., FPGAs). To address the issue, we propose a resource-efficient, scalable, and order-agnostic hardware design and its implementation by examining and integrating two key concepts, called Window-ID and Pane, which are originally proposed for software implementation, respectively. Evaluation results show that the proposed implementation scales well compared to the previous FPGA implementation in terms of both resource consumption and performance. The proposed design is fully pipelined and our implementation can process out-of-order data items, or tuples, at wire speed up to 200 million tuples per second.

Original languageEnglish
Title of host publicationProceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013
Pages112-121
Number of pages10
DOIs
Publication statusPublished - 2013 Dec 1
Externally publishedYes
Event2013 1st International Symposium on Computing and Networking, CANDAR 2013 - Matsuyama, Ehime, Japan
Duration: 2013 Dec 42013 Dec 6

Other

Other2013 1st International Symposium on Computing and Networking, CANDAR 2013
CountryJapan
CityMatsuyama, Ehime
Period13/12/413/12/6

Fingerprint

Field programmable gate arrays (FPGA)
Hardware
Particle accelerators
Scalability
Wire
Processing

Keywords

  • aggregation
  • data stream processing
  • disordered data
  • FPGA
  • sliding window
  • stream punctuation

ASJC Scopus subject areas

  • Computer Networks and Communications

Cite this

Oge, Y., Yoshimi, M., Miyoshi, T., Kawashima, H., Irie, H., & Yoshinaga, T. (2013). An efficient and scalable implementation of sliding-window aggregate operator on FPGA. In Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013 (pp. 112-121). [6726885] https://doi.org/10.1109/CANDAR.2013.23

An efficient and scalable implementation of sliding-window aggregate operator on FPGA. / Oge, Yasin; Yoshimi, Masato; Miyoshi, Takefumi; Kawashima, Hideyuki; Irie, Hidetsugu; Yoshinaga, Tsutomu.

Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013. 2013. p. 112-121 6726885.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Oge, Y, Yoshimi, M, Miyoshi, T, Kawashima, H, Irie, H & Yoshinaga, T 2013, An efficient and scalable implementation of sliding-window aggregate operator on FPGA. in Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013., 6726885, pp. 112-121, 2013 1st International Symposium on Computing and Networking, CANDAR 2013, Matsuyama, Ehime, Japan, 13/12/4. https://doi.org/10.1109/CANDAR.2013.23
Oge Y, Yoshimi M, Miyoshi T, Kawashima H, Irie H, Yoshinaga T. An efficient and scalable implementation of sliding-window aggregate operator on FPGA. In Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013. 2013. p. 112-121. 6726885 https://doi.org/10.1109/CANDAR.2013.23
Oge, Yasin ; Yoshimi, Masato ; Miyoshi, Takefumi ; Kawashima, Hideyuki ; Irie, Hidetsugu ; Yoshinaga, Tsutomu. / An efficient and scalable implementation of sliding-window aggregate operator on FPGA. Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013. 2013. pp. 112-121
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