TY - GEN
T1 - An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings
AU - Ohwada, Ayaka
AU - Kojima, Takuya
AU - Amano, Hideharu
N1 - Funding Information:
ACKNOWLEDGMENT This work was partly supported by JST CREST Grant Number JPMJCR19K1, Japan. We would like to thank all those involved.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - In recent years, IoT devices have become widespread, and energy-efficient coarse-grained reconfigurable architectures (CGRAs) have attracted attention. CGRAs comprise several processing units called processing elements (PEs) arranged in a two-dimensional array. The operations of PEs and the interconnections between them are adaptively changed depending on a target application, and this contributes to a higher energy efficiency compared to general-purpose processors. The application kernel executed on CGRAs is represented as a data flow graph (DFG), and CGRA compilers are responsible for mapping the DFG onto the PE array. Thus, mapping algorithms significantly influence the performance and power efficiency of CGRAs as well as the compile time. This paper proposes POCOCO, a compiler framework for CGRAs that can use pre-optimized subgraph mappings. This contributes to reducing the compiler optimization task. To leverage the subgraph mappings, we extend an existing mapping method based on a genetic algorithm. Experiments on three architectures demonstrated that the proposed method reduces the optimization time by 48%, on an average, for the best case of the three architectures.
AB - In recent years, IoT devices have become widespread, and energy-efficient coarse-grained reconfigurable architectures (CGRAs) have attracted attention. CGRAs comprise several processing units called processing elements (PEs) arranged in a two-dimensional array. The operations of PEs and the interconnections between them are adaptively changed depending on a target application, and this contributes to a higher energy efficiency compared to general-purpose processors. The application kernel executed on CGRAs is represented as a data flow graph (DFG), and CGRA compilers are responsible for mapping the DFG onto the PE array. Thus, mapping algorithms significantly influence the performance and power efficiency of CGRAs as well as the compile time. This paper proposes POCOCO, a compiler framework for CGRAs that can use pre-optimized subgraph mappings. This contributes to reducing the compiler optimization task. To leverage the subgraph mappings, we extend an existing mapping method based on a genetic algorithm. Experiments on three architectures demonstrated that the proposed method reduces the optimization time by 48%, on an average, for the best case of the three architectures.
KW - coarse grained reconfigurable architectures
KW - compiler
UR - http://www.scopus.com/inward/record.url?scp=85129588644&partnerID=8YFLogxK
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U2 - 10.1109/PDP55904.2022.00010
DO - 10.1109/PDP55904.2022.00010
M3 - Conference contribution
AN - SCOPUS:85129588644
T3 - Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022
SP - 1
EP - 9
BT - Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022
A2 - Gonzalez-Escribano, Arturo
A2 - Garcia, Jose Daniel
A2 - Torquati, Massimo
A2 - Skavhaug, Amund
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022
Y2 - 9 March 2022 through 11 March 2022
ER -
