Inductive-coupling link between stacked chips in a package communicates by using coils made by on-chip Interconnections. An XY-coil layout style allows logic interconnections to go through the coil, which significantly saves Interconnection resources consumed by the coil. However, the logic interconnections generate capacitive-coupling noise on the coil and degrade signal in the inductive-coupling link. In this paper, an extended XY coil with ground shields is presented for noise reduction. Simulation study shows that the noise voltage is reduced to 1/5 of the conventional XY coil. This noise reduction enables to reduce transmit power required for the same BER. Test-chip measurement in 0.18μm CMOS demonstrates that the transmit power at 1Gb/s with BER<10-12 is reduced by 60% compared to the conventional XY coil.