AN FPGA ACCELERATION AND OPTIMIZATION TECHNIQUES FOR 2D LIDAR SLAM ALGORITHM

Keisuke Sugiura, Hiroki Matsutani

Research output: Contribution to journalArticlepeer-review

Abstract

An efficient hardware design of Simultaneous Localization and Mapping (SLAM) methods is of necessity for mobile autonomous robots with limited computational resources. In this paper, we develop a resource-efficient FPGA design for accelerating the scan matching process, which typically exhibits the bottleneck in 2D LiDAR SLAM methods. Scan matching is a process of correcting a robot pose by aligning the latest LiDAR measurements with an occupancy grid map, which encodes the information about the surrounding environment. The proposed design exploits an inherent parallelism in the Rao-Blackwellized Particle Filter (RBPF) based algorithms to perform scan matching computations for multiple particles in parallel. In the design, map compression technique and lookup-table are employed to reduce the resource utilization and achieve the maximum throughput. Simulation results using the benchmark datasets show that the scan matching is accelerated by 23.3–51.1× and the overall throughput is improved by 1.97–3.16× without seriously degrading the quality of the final outputs. Furthermore, our implementation requires only 37% of the total resources available in the Xilinx ZCU104 evaluation board, thus providing a feasible solution to realize SLAM applications on indoor mobile robots.

Original languageEnglish
JournalUnknown Journal
Publication statusPublished - 2020 May 29

Keywords

  • SLAM · GMapping · SoC · FPGA

ASJC Scopus subject areas

  • General

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