Abstract
As data sets grow rapidly in size and the number, an outlier detection that filters unnecessary normal information becomes important. In this paper, we propose to move the outlier detection from an application layer to a NIC (Network Interface Card). Only anomalous items or events are delivered for a network protocol stack and the other packets are discarded at the NIC. The demands for storage and computation costs at a host are thus drastically reduced. We employ lazy learning algorithms for the outlier detection, because they can be applied to complex reference data including different clusters. However, it is challenging to offload the lazy learning to NIC hardware because of high computational cost and huge reference data. In this paper, we propose to cache only a frequently-Accessed portion of reference data in the NIC. This idea can be applied to lazy learning algorithms in general. LOF (Local Outlier Factor) and KNN (K-Nearest Neighbor) are thus implemented on an FPGA (Field Programmable Gate Arrays) based NIC. Simulation results of the proposed system using LOF with 100,000 reference data show that 45% to 90% of queries are hit to the proposed cache and filtered at the NIC. The results are corresponding to 1.82x to 10x throughput improvements on the outlier filtering compared to that of a software-based execution.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 15-22 |
| Number of pages | 8 |
| ISBN (Electronic) | 9781509060580 |
| DOIs | |
| Publication status | Published - 2017 Apr 26 |
| Event | 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017 - St. Petersburg, Russian Federation Duration: 2017 Mar 6 → 2017 Mar 8 |
Other
| Other | 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017 |
|---|---|
| Country | Russian Federation |
| City | St. Petersburg |
| Period | 17/3/6 → 17/3/8 |
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Keywords
- FPGA NIC
- K Nearest Neighbor
- Lazy Learning
- Local Outlier Factor
- Outlier Detection
ASJC Scopus subject areas
- Computer Networks and Communications
- Hardware and Architecture
- Information Systems and Management
Cite this
An FPGA-based In-NIC Cache Approach for Lazy Learning Outlier Filtering. / Hayashi, Ami; Matsutani, Hiroki.
Proceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 15-22 7912620.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - An FPGA-based In-NIC Cache Approach for Lazy Learning Outlier Filtering
AU - Hayashi, Ami
AU - Matsutani, Hiroki
PY - 2017/4/26
Y1 - 2017/4/26
N2 - As data sets grow rapidly in size and the number, an outlier detection that filters unnecessary normal information becomes important. In this paper, we propose to move the outlier detection from an application layer to a NIC (Network Interface Card). Only anomalous items or events are delivered for a network protocol stack and the other packets are discarded at the NIC. The demands for storage and computation costs at a host are thus drastically reduced. We employ lazy learning algorithms for the outlier detection, because they can be applied to complex reference data including different clusters. However, it is challenging to offload the lazy learning to NIC hardware because of high computational cost and huge reference data. In this paper, we propose to cache only a frequently-Accessed portion of reference data in the NIC. This idea can be applied to lazy learning algorithms in general. LOF (Local Outlier Factor) and KNN (K-Nearest Neighbor) are thus implemented on an FPGA (Field Programmable Gate Arrays) based NIC. Simulation results of the proposed system using LOF with 100,000 reference data show that 45% to 90% of queries are hit to the proposed cache and filtered at the NIC. The results are corresponding to 1.82x to 10x throughput improvements on the outlier filtering compared to that of a software-based execution.
AB - As data sets grow rapidly in size and the number, an outlier detection that filters unnecessary normal information becomes important. In this paper, we propose to move the outlier detection from an application layer to a NIC (Network Interface Card). Only anomalous items or events are delivered for a network protocol stack and the other packets are discarded at the NIC. The demands for storage and computation costs at a host are thus drastically reduced. We employ lazy learning algorithms for the outlier detection, because they can be applied to complex reference data including different clusters. However, it is challenging to offload the lazy learning to NIC hardware because of high computational cost and huge reference data. In this paper, we propose to cache only a frequently-Accessed portion of reference data in the NIC. This idea can be applied to lazy learning algorithms in general. LOF (Local Outlier Factor) and KNN (K-Nearest Neighbor) are thus implemented on an FPGA (Field Programmable Gate Arrays) based NIC. Simulation results of the proposed system using LOF with 100,000 reference data show that 45% to 90% of queries are hit to the proposed cache and filtered at the NIC. The results are corresponding to 1.82x to 10x throughput improvements on the outlier filtering compared to that of a software-based execution.
KW - FPGA NIC
KW - K Nearest Neighbor
KW - Lazy Learning
KW - Local Outlier Factor
KW - Outlier Detection
UR - http://www.scopus.com/inward/record.url?scp=85019543875&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85019543875&partnerID=8YFLogxK
U2 - 10.1109/PDP.2017.48
DO - 10.1109/PDP.2017.48
M3 - Conference contribution
SP - 15
EP - 22
BT - Proceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017
PB - Institute of Electrical and Electronics Engineers Inc.
ER -