An FPGA implementation of reconfigurable real-time vision architecture

Jorge Hiraiwa, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

A video processing architecture based on FPGA for real-time embedded vision systems is proposed in this paper. Recently, embedded vision systems are used in various applications. On the other hand, the throughput required to the system has been increasing as the high-definition vision replaces the current vision systems. Since more complex vision algorithms become available, higher performance and better expandability are requested accordingly. As a solution for this challenging situation, FPGA is now drawing more attention as an embedded vision system platform. In addition, high-level synthesis design is preferred instead of traditional low-level design based on hardware description languages with lower productivity. In this study, we implemented a video processing pipelined architecture which can offer flexibility for interchange processing modules. Each module was implemented using Verilog HDL and Vivado HLS for its evaluation.

Original languageEnglish
Title of host publicationProceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013
Pages150-155
Number of pages6
DOIs
Publication statusPublished - 2013 Aug 19
Event27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013 - Barcelona, Spain
Duration: 2013 Mar 252013 Mar 28

Publication series

NameProceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013

Other

Other27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013
CountrySpain
CityBarcelona
Period13/3/2513/3/28

Keywords

  • Embedded Vision System
  • FPGA
  • High Level Synthesis
  • Real-Time Vision Architecture
  • Video Processing Pipeline

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications

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  • Cite this

    Hiraiwa, J., & Amano, H. (2013). An FPGA implementation of reconfigurable real-time vision architecture. In Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013 (pp. 150-155). [6550388] (Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013). https://doi.org/10.1109/WAINA.2013.131