An FPGA NIC Based Hardware Caching for Blockchain

Yuma Sakakibara, Kohei Nakamura, Hiroki Matsutani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

These days, people pay attention to Blockchain, which is a main technology of cryptocurrency. Blockchain is a fault-tolerant distributed ledger that does not need an administrator. We call transfer of digital asset as a “transaction”. We need to hold all transactions to use Blockchain. Therefore, the amount of Blockchain data increases as time proceeds. On the other hand, the number of Internet of Things (IoT) products has been increasing. It is difficult for IoT products to hold all Blockchain data because of their data capacity. Thus, they access Blockchain network via servers that have enough data capacity. More and more IoT products will join Blockchain network via servers, so it is useful to reduce workloads and improve throughput. In this paper, we propose caching technique using a Field Programmable Gate Array-based (FPGA) Network Interface Card (NIC) that has 10Gigabit Ethernet (10GbE) interfaces. FPGA NIC instead of the server responds to requests from IoT products if the cache hits. The proposed system can reduce server workloads. We implemented the proposed hardware cache to achieve high throughput on NetFPGA-10G board. We counted the number of requests that the Blockchain server processed at a given time and calculated throughput as evaluation. Throughput improved from 6.73 to 7.45 times when hitting the cache.

Original languageEnglish
Title of host publicationProceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017
PublisherAssociation for Computing Machinery
ISBN (Electronic)9781450353168
DOIs
Publication statusPublished - 2017 Jun 7
Event8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017 - Bochum, Germany
Duration: 2017 Jun 72017 Jun 9

Other

Other8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017
CountryGermany
CityBochum
Period17/6/717/6/9

Fingerprint

Computer hardware
Interfaces (computer)
Field programmable gate arrays (FPGA)
Servers
Throughput
Ethernet
Internet of things

Keywords

  • 10Gbit Ethernet
  • Blockchain
  • FPGAs

ASJC Scopus subject areas

  • Human-Computer Interaction
  • Computer Networks and Communications
  • Computer Vision and Pattern Recognition
  • Software

Cite this

Sakakibara, Y., Nakamura, K., & Matsutani, H. (2017). An FPGA NIC Based Hardware Caching for Blockchain. In Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017 [1] Association for Computing Machinery. https://doi.org/10.1145/3120895.3120897

An FPGA NIC Based Hardware Caching for Blockchain. / Sakakibara, Yuma; Nakamura, Kohei; Matsutani, Hiroki.

Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery, 2017. 1.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sakakibara, Y, Nakamura, K & Matsutani, H 2017, An FPGA NIC Based Hardware Caching for Blockchain. in Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017., 1, Association for Computing Machinery, 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017, Bochum, Germany, 17/6/7. https://doi.org/10.1145/3120895.3120897
Sakakibara Y, Nakamura K, Matsutani H. An FPGA NIC Based Hardware Caching for Blockchain. In Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery. 2017. 1 https://doi.org/10.1145/3120895.3120897
Sakakibara, Yuma ; Nakamura, Kohei ; Matsutani, Hiroki. / An FPGA NIC Based Hardware Caching for Blockchain. Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery, 2017.
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