TY - GEN
T1 - An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board
AU - Chen, Yuchen
AU - Wei, Kaijie
AU - Nishi, Hiroaki
AU - Amano, Hideharu
N1 - Funding Information:
This work was supported by JST, CREST Grant Number JP-MJCR19K1, Japan.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Object detection and tracking technology are essential in many ways with the increasing demand for remote video conferencing and video surveillance. This paper focuses on a method that combines an object detection method based on a CNN (Convolutional Neural Network) with a motion-vector-based object tracking method in specified frames instead of the whole frame stream. Although this method can improve the throughput with a small memory requirement, it requires 3D image filters to reduce the noise in each motion vector. The immense computing power needed for 3D image filters prevents this method from being popularly used. To address this problem, we propose to implement the technique on an FPGA and offload the filters and CNN engine on the FPGA hardwired logic. We implemented slide window-based image filters on a Zynq Ultrascale+ FPGA board and achieved 23.42 times performance improvement for the median filter and 55.46 times for the average filter, respectively. Considering the resource usage, it appeared that we could implement these 3D image filters design with YOLO on the target FPGA.
AB - Object detection and tracking technology are essential in many ways with the increasing demand for remote video conferencing and video surveillance. This paper focuses on a method that combines an object detection method based on a CNN (Convolutional Neural Network) with a motion-vector-based object tracking method in specified frames instead of the whole frame stream. Although this method can improve the throughput with a small memory requirement, it requires 3D image filters to reduce the noise in each motion vector. The immense computing power needed for 3D image filters prevents this method from being popularly used. To address this problem, we propose to implement the technique on an FPGA and offload the filters and CNN engine on the FPGA hardwired logic. We implemented slide window-based image filters on a Zynq Ultrascale+ FPGA board and achieved 23.42 times performance improvement for the median filter and 55.46 times for the average filter, respectively. Considering the resource usage, it appeared that we could implement these 3D image filters design with YOLO on the target FPGA.
KW - FPGA
KW - image filter
KW - motion vector
KW - slide window
KW - Vivado HLS
UR - http://www.scopus.com/inward/record.url?scp=85148598318&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85148598318&partnerID=8YFLogxK
U2 - 10.1109/CANDAR57322.2022.00018
DO - 10.1109/CANDAR57322.2022.00018
M3 - Conference contribution
AN - SCOPUS:85148598318
T3 - Proceedings - 2022 10th International Symposium on Computing and Networking, CANDAR 2022
SP - 83
EP - 89
BT - Proceedings - 2022 10th International Symposium on Computing and Networking, CANDAR 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 10th International Symposium on Computing and Networking, CANDAR 2022
Y2 - 21 November 2022 through 22 November 2022
ER -