An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips

Junichiro Kadomoto, Tomoki Miyata, Hideharu Amano, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A wireless vertical bus with collision detection scheme for 3-D network-on-chips (NoC) is presented. Utilizing inductive-coupling between coils, wireless connection between all stacked chips is established. Data collision is detected by sensing magnetic field variation. A test chip is fabricated in 65 nm SOI CMOS technology. A data rate of 0.8 Gb/s with a BER < 10-12 is achieved. The energy efficiency is better than 1.4 pJ/b. A collision detection circuit is implemented and its operation is confirmed.

Original languageEnglish
Title of host publication2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages41-44
Number of pages4
ISBN (Electronic)9781509037001
DOIs
Publication statusPublished - 2017 Feb 6
Event12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Toyama, Japan
Duration: 2016 Nov 72016 Nov 9

Other

Other12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016
CountryJapan
CityToyama
Period16/11/716/11/9

Fingerprint

Magnetic fields
Energy efficiency
Networks (circuits)
Network-on-chip

Keywords

  • 3-D integration
  • collision detection
  • inductive-coupling bus
  • Network-on-chips (NoC)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Kadomoto, J., Miyata, T., Amano, H., & Kuroda, T. (2017). An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. In 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings (pp. 41-44). [7844130] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2016.7844130

An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. / Kadomoto, Junichiro; Miyata, Tomoki; Amano, Hideharu; Kuroda, Tadahiro.

2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 41-44 7844130.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kadomoto, J, Miyata, T, Amano, H & Kuroda, T 2017, An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. in 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings., 7844130, Institute of Electrical and Electronics Engineers Inc., pp. 41-44, 12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, 16/11/7. https://doi.org/10.1109/ASSCC.2016.7844130
Kadomoto J, Miyata T, Amano H, Kuroda T. An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. In 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 41-44. 7844130 https://doi.org/10.1109/ASSCC.2016.7844130
Kadomoto, Junichiro ; Miyata, Tomoki ; Amano, Hideharu ; Kuroda, Tadahiro. / An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 41-44
@inproceedings{8d41f77721034e7c96b50dbf6a222a33,
title = "An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips",
abstract = "A wireless vertical bus with collision detection scheme for 3-D network-on-chips (NoC) is presented. Utilizing inductive-coupling between coils, wireless connection between all stacked chips is established. Data collision is detected by sensing magnetic field variation. A test chip is fabricated in 65 nm SOI CMOS technology. A data rate of 0.8 Gb/s with a BER < 10-12 is achieved. The energy efficiency is better than 1.4 pJ/b. A collision detection circuit is implemented and its operation is confirmed.",
keywords = "3-D integration, collision detection, inductive-coupling bus, Network-on-chips (NoC)",
author = "Junichiro Kadomoto and Tomoki Miyata and Hideharu Amano and Tadahiro Kuroda",
year = "2017",
month = "2",
day = "6",
doi = "10.1109/ASSCC.2016.7844130",
language = "English",
pages = "41--44",
booktitle = "2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips

AU - Kadomoto, Junichiro

AU - Miyata, Tomoki

AU - Amano, Hideharu

AU - Kuroda, Tadahiro

PY - 2017/2/6

Y1 - 2017/2/6

N2 - A wireless vertical bus with collision detection scheme for 3-D network-on-chips (NoC) is presented. Utilizing inductive-coupling between coils, wireless connection between all stacked chips is established. Data collision is detected by sensing magnetic field variation. A test chip is fabricated in 65 nm SOI CMOS technology. A data rate of 0.8 Gb/s with a BER < 10-12 is achieved. The energy efficiency is better than 1.4 pJ/b. A collision detection circuit is implemented and its operation is confirmed.

AB - A wireless vertical bus with collision detection scheme for 3-D network-on-chips (NoC) is presented. Utilizing inductive-coupling between coils, wireless connection between all stacked chips is established. Data collision is detected by sensing magnetic field variation. A test chip is fabricated in 65 nm SOI CMOS technology. A data rate of 0.8 Gb/s with a BER < 10-12 is achieved. The energy efficiency is better than 1.4 pJ/b. A collision detection circuit is implemented and its operation is confirmed.

KW - 3-D integration

KW - collision detection

KW - inductive-coupling bus

KW - Network-on-chips (NoC)

UR - http://www.scopus.com/inward/record.url?scp=85015235856&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85015235856&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2016.7844130

DO - 10.1109/ASSCC.2016.7844130

M3 - Conference contribution

SP - 41

EP - 44

BT - 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

ER -