An inductive-coupling DC voltage transceiver for highly parallel wafer-level testing

Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 μm × 100 μm). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution.

Original languageEnglish
Article number5584951
Pages (from-to)2057-2065
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume45
Issue number10
DOIs
Publication statusPublished - 2010 Oct

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Transceivers
Testing
Electric potential
Calibration
Networks (circuits)
Digital circuits
Feedback
Costs

Keywords

  • DC test
  • inductive coupling
  • parallel test
  • transceiver
  • wafer test

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

An inductive-coupling DC voltage transceiver for highly parallel wafer-level testing. / Yoshida, Yoichi; Nose, Koichi; Nakagawa, Yoshihiro; Noguchi, Koichiro; Morita, Yasuhiro; Tago, Masamoto; Mizuno, Masayuki; Kuroda, Tadahiro.

In: IEEE Journal of Solid-State Circuits, Vol. 45, No. 10, 5584951, 10.2010, p. 2057-2065.

Research output: Contribution to journalArticle

Yoshida, Y, Nose, K, Nakagawa, Y, Noguchi, K, Morita, Y, Tago, M, Mizuno, M & Kuroda, T 2010, 'An inductive-coupling DC voltage transceiver for highly parallel wafer-level testing', IEEE Journal of Solid-State Circuits, vol. 45, no. 10, 5584951, pp. 2057-2065. https://doi.org/10.1109/JSSC.2010.2061653
Yoshida, Yoichi ; Nose, Koichi ; Nakagawa, Yoshihiro ; Noguchi, Koichiro ; Morita, Yasuhiro ; Tago, Masamoto ; Mizuno, Masayuki ; Kuroda, Tadahiro. / An inductive-coupling DC voltage transceiver for highly parallel wafer-level testing. In: IEEE Journal of Solid-State Circuits. 2010 ; Vol. 45, No. 10. pp. 2057-2065.
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