An inductive-coupling DC voltage transceiver for highly parallel wafer-level testing

Yoichi Yoshida; Koichi Nose; Yoshihiro Nakagawa; Koichiro Noguchi; Yasuhiro Morita; Masamoto Tago; Masayuki Mizuno; Tadahiro Kuroda

doi:10.1109/JSSC.2010.2061653

An inductive-coupling DC voltage transceiver for highly parallel wafer-level testing

Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda

Research output: Contribution to journal › Article › peer-review

10 Citations (Scopus)

Abstract

A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 μm × 100 μm). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution.

Original language	English
Article number	5584951
Pages (from-to)	2057-2065
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	45
Issue number	10
DOIs	https://doi.org/10.1109/JSSC.2010.2061653
Publication status	Published - 2010 Oct

Keywords

DC test
inductive coupling
parallel test
transceiver
wafer test

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2010.2061653

Cite this

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abstract = "A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 μm × 100 μm). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution.",

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AU - Yoshida, Yoichi

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AU - Nakagawa, Yoshihiro

AU - Noguchi, Koichiro

AU - Morita, Yasuhiro

AU - Tago, Masamoto

AU - Mizuno, Masayuki

AU - Kuroda, Tadahiro

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KW - parallel test

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An inductive-coupling DC voltage transceiver for highly parallel wafer-level testing

Abstract

Keywords

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