TY - GEN
T1 - An I/O mechanism on a dynamically reconfigurable processor - Which should be moved
T2 - 2005 International Conference on Field Programmable Logic and Applications, FPL
AU - Amano, Hideharu
AU - Abe, Shohei
AU - Deguchi, Katsuaki
AU - Hasegawa, Yohei
PY - 2005/12/1
Y1 - 2005/12/1
N2 - In some applications on Dynamically Reconfigurable Processor (DRP), the input/output of data stream occupies about 20% of total execution time. In order to hide the overhead of input/output, the separation of the I/O context and double-buffering mechanism are proposed. Using the mechanism, I/O overhead of six streaming processing programs can be completely hidden. Based on the analysis of I/O performance, two alternatives for executing parallel processing with multiple DRP Cores are compared and discussed.
AB - In some applications on Dynamically Reconfigurable Processor (DRP), the input/output of data stream occupies about 20% of total execution time. In order to hide the overhead of input/output, the separation of the I/O context and double-buffering mechanism are proposed. Using the mechanism, I/O overhead of six streaming processing programs can be completely hidden. Based on the analysis of I/O performance, two alternatives for executing parallel processing with multiple DRP Cores are compared and discussed.
UR - http://www.scopus.com/inward/record.url?scp=33746883577&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33746883577&partnerID=8YFLogxK
U2 - 10.1109/FPL.2005.1515746
DO - 10.1109/FPL.2005.1515746
M3 - Conference contribution
AN - SCOPUS:33746883577
SN - 0780393627
SN - 9780780393622
T3 - Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL
SP - 347
EP - 352
BT - Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL
Y2 - 24 August 2005 through 26 August 2005
ER -