An On-Chip Scalable Low Power Consumption High-Voltage Driver Based on Standard CMOS Technology

Jorge Canada; Yui Yoshida; Hiroki Miura; Nobuhiko Nakano

doi:10.1109/ISOCC50952.2020.9333001

An On-Chip Scalable Low Power Consumption High-Voltage Driver Based on Standard CMOS Technology

Jorge Canada, Yui Yoshida, Hiroki Miura, Nobuhiko Nakano

Department of Electronics and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A scalable low power consumption high-voltage driver comprising only standard low-voltage CMOS transistors is proposed. The circuit is a Stacked MOSFET high-voltage driver. The proposed design stands out for its low power consumption (in the order of microwatts), small area, scalability and self-sufficiency. The main setbacks to be considered are its low switching speed, in the order of microseconds, and the fact that its applicability is limited to capacitive loads and high resistive loads. This paper reports simulation results obtained through the implementation of multiple designs in 0.18 um CMOS technology.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	17-18
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9333001
Publication status	Published - 2020 Oct 21
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 2020 Oct 21 → 2020 Oct 24

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	20/10/21 → 20/10/24

Keywords

high voltage driver
low power consumption
on-chip
stacked MOSFET
standard CMOS

ASJC Scopus subject areas

Energy Engineering and Power Technology
Electrical and Electronic Engineering
Instrumentation
Artificial Intelligence
Hardware and Architecture

Access to Document

10.1109/ISOCC50952.2020.9333001

Cite this

Canada, J., Yoshida, Y., Miura, H., & Nakano, N. (2020). An On-Chip Scalable Low Power Consumption High-Voltage Driver Based on Standard CMOS Technology. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 17-18). [9333001] (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9333001

An On-Chip Scalable Low Power Consumption High-Voltage Driver Based on Standard CMOS Technology. / Canada, Jorge; Yoshida, Yui; Miura, Hiroki et al.

Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 17-18 9333001 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Canada, J, Yoshida, Y, Miura, H & Nakano, N 2020, An On-Chip Scalable Low Power Consumption High-Voltage Driver Based on Standard CMOS Technology. in Proceedings - International SoC Design Conference, ISOCC 2020., 9333001, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 17-18, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 20/10/21. https://doi.org/10.1109/ISOCC50952.2020.9333001

Canada J, Yoshida Y, Miura H, Nakano N. An On-Chip Scalable Low Power Consumption High-Voltage Driver Based on Standard CMOS Technology. In Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 17-18. 9333001. (Proceedings - International SoC Design Conference, ISOCC 2020). doi: 10.1109/ISOCC50952.2020.9333001

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abstract = "A scalable low power consumption high-voltage driver comprising only standard low-voltage CMOS transistors is proposed. The circuit is a Stacked MOSFET high-voltage driver. The proposed design stands out for its low power consumption (in the order of microwatts), small area, scalability and self-sufficiency. The main setbacks to be considered are its low switching speed, in the order of microseconds, and the fact that its applicability is limited to capacitive loads and high resistive loads. This paper reports simulation results obtained through the implementation of multiple designs in 0.18 um CMOS technology. ",

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An On-Chip Scalable Low Power Consumption High-Voltage Driver Based on Standard CMOS Technology

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

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