An on-chip self-powered non-volatile one-time-programmable memory system in standard CMOS technology

Jorge Canada, Yui Yoshida, Hiroki Miura, Nobuhiko Nakano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An on-chip self-powered memory system fully realizable in standard CMOS technology is presented. The memory cells consist of a MOS capacitor operated as an antifuse, which is written by applying high voltage between its terminals during tens of milliseconds. The full system comprises an on-chip solar cell, a cross coupled charge pump DC-DC converter, stacked MOSFET high voltage drivers and CMOS anti-fuse one-time programmable memory cells. The writing of each memory cell can be commanded through a digital signal provided by an on-chip control circuit or other on-chip sensors. The proposed memory system is intended to be integrated in small autonomous on-chip devices. This paper describes each of the components that build up the proposed system and demonstrates its feasibility through results of its implementation in 0.18 um CMOS technology.

Original languageEnglish
Title of host publicationICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728160443
DOIs
Publication statusPublished - 2020 Nov 23
Event27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020 - Glasgow, United Kingdom
Duration: 2020 Nov 232020 Nov 25

Publication series

NameICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings

Conference

Conference27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020
CountryUnited Kingdom
CityGlasgow
Period20/11/2320/11/25

Keywords

  • CMOS anti-fuse
  • Low power consumption
  • Non-volatile memory
  • OTP memory
  • On-chip
  • Standard CMOS

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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