An On-Chip Ultra-Low-Power Hz-Range Ring Oscillator Based on Dynamic Leakage Suppression Logic

Jorge Canada, Yui Yoshida, Hiroki Miura, Nobuhiko Nakano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, simulation and experimental results of an ultra-low-power Hz-range ring oscillator are presented. The proposed circuit can operate from subthreshold voltage (0.24 V) to nominal voltage (1.8 V) and reaches power consumptions in the picowatt order. The design, based on Dynamic Leakage Suppression (DLS) logic, has been implemented in 0.18 um CMOS technology and uses sub-pF capacitors. Its main features are its low power consumption, small area, wide supply voltage range and utmost simplicity.

Original languageEnglish
Title of host publicationITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages378-383
Number of pages6
ISBN (Electronic)9784885523281
Publication statusPublished - 2020 Jul
Event35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020 - Nagoya, Japan
Duration: 2020 Jul 32020 Jul 6

Publication series

NameITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications

Conference

Conference35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020
CountryJapan
CityNagoya
Period20/7/320/7/6

Keywords

  • DLS
  • Hz-range
  • on-chip
  • ring oscillator
  • sub-nW

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Information Systems and Management
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'An On-Chip Ultra-Low-Power Hz-Range Ring Oscillator Based on Dynamic Leakage Suppression Logic'. Together they form a unique fingerprint.

Cite this