An outside-rail opamp design relaxing low-voltage constraint on future scaled transistors

Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, Takayasu Sakurai

    Research output: Contribution to journalArticle


    An opamp design with outside-rail output relaxing a low-voltage constraint on future scaled transistors is presented. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8-V 0.18-μm standard CMOS process. The 3-V-output operation is experimentally verified. The outside-rail output design with scaled transistors shows area advantage over un-scaled and inside-rail design while keeping signal-to-noise ratio and gain bandwidth constant. The chip area is estimated to be 47 of the conventional opamp using a 0.35-μm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-μm CMOS design due to reduced capacitor area. The proposed design could be extended to n-tuple V DD operation and applied to circuits with a feed back loop such as gain stage and filters. The extendibility of n-tuple VDD operation and its application are discussed with simulation results.

    Original languageEnglish
    Pages (from-to)786-792
    Number of pages7
    JournalIEICE Transactions on Electronics
    Issue number4
    Publication statusPublished - 2007 Apr


    • Opamp
    • Outside-rail
    • Scaling

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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