An outside-rail opamp design targeting for future scaled transistors

Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

An outside-rail output opamp targeting for future scaled MOSFETs is designed and the 3-V-output operation is successfully verified using 1.8-V standard CMOS process. This is the first experimental verification of an outside-rail opamp design which shows area advantage over un-scaled and insiderail design while keeping signal-to-noise ratio and gain bandwidth constant. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8V 0.18-μm standard CMOS process. The chip area is estimated to be 47% of the conventional opamp using a 0.35-μm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-mμ CMOS design due to reduced capacitor area.

Original languageEnglish
Title of host publication2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Pages73-76
Number of pages4
DOIs
Publication statusPublished - 2006
Externally publishedYes
Event1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan, Province of China
Duration: 2005 Nov 12005 Nov 3

Other

Other1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
CountryTaiwan, Province of China
CityHsinchu
Period05/11/105/11/3

Fingerprint

Operational amplifiers
Rails
Transistors
Oxides
Signal to noise ratio
Capacitors
Bandwidth

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Ishida, K., Tamtrakarn, A., Sakurai, T., & Ishikuro, H. (2006). An outside-rail opamp design targeting for future scaled transistors. In 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005 (pp. 73-76). [4017534] https://doi.org/10.1109/ASSCC.2005.251810

An outside-rail opamp design targeting for future scaled transistors. / Ishida, Koichi; Tamtrakarn, Atit; Sakurai, Takayasu; Ishikuro, Hiroki.

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. 2006. p. 73-76 4017534.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ishida, K, Tamtrakarn, A, Sakurai, T & Ishikuro, H 2006, An outside-rail opamp design targeting for future scaled transistors. in 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005., 4017534, pp. 73-76, 1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005, Hsinchu, Taiwan, Province of China, 05/11/1. https://doi.org/10.1109/ASSCC.2005.251810
Ishida K, Tamtrakarn A, Sakurai T, Ishikuro H. An outside-rail opamp design targeting for future scaled transistors. In 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. 2006. p. 73-76. 4017534 https://doi.org/10.1109/ASSCC.2005.251810
Ishida, Koichi ; Tamtrakarn, Atit ; Sakurai, Takayasu ; Ishikuro, Hiroki. / An outside-rail opamp design targeting for future scaled transistors. 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. 2006. pp. 73-76
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