An outside-rail opamp design targeting for future scaled transistors

Koichi Ishida; Atit Tamtrakarn; Takayasu Sakurai; Hiroki Ishikuro

doi:10.1109/ASSCC.2005.251810

An outside-rail opamp design targeting for future scaled transistors

Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

An outside-rail output opamp targeting for future scaled MOSFETs is designed and the 3-V-output operation is successfully verified using 1.8-V standard CMOS process. This is the first experimental verification of an outside-rail opamp design which shows area advantage over un-scaled and insiderail design while keeping signal-to-noise ratio and gain bandwidth constant. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8V 0.18-μm standard CMOS process. The chip area is estimated to be 47% of the conventional opamp using a 0.35-μm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-mμ CMOS design due to reduced capacitor area.

Original language	English
Title of host publication	2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Publisher	IEEE Computer Society
Pages	73-76
Number of pages	4
ISBN (Print)	0780391624, 9780780391628
DOIs	https://doi.org/10.1109/ASSCC.2005.251810
Publication status	Published - 2005
Externally published	Yes
Event	1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan, Province of China Duration: 2005 Nov 1 → 2005 Nov 3

Publication series

Name	2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Other

Other	1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	05/11/1 → 05/11/3

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ASSCC.2005.251810

Cite this

An outside-rail opamp design targeting for future scaled transistors. / Ishida, Koichi; Tamtrakarn, Atit; Sakurai, Takayasu et al.

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. IEEE Computer Society, 2005. p. 73-76 4017534 (2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ishida, K, Tamtrakarn, A, Sakurai, T & Ishikuro, H 2005, An outside-rail opamp design targeting for future scaled transistors. in 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005., 4017534, 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005, IEEE Computer Society, pp. 73-76, 1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005, Hsinchu, Taiwan, Province of China, 05/11/1. https://doi.org/10.1109/ASSCC.2005.251810

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abstract = "An outside-rail output opamp targeting for future scaled MOSFETs is designed and the 3-V-output operation is successfully verified using 1.8-V standard CMOS process. This is the first experimental verification of an outside-rail opamp design which shows area advantage over un-scaled and insiderail design while keeping signal-to-noise ratio and gain bandwidth constant. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8V 0.18-μm standard CMOS process. The chip area is estimated to be 47% of the conventional opamp using a 0.35-μm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-mμ CMOS design due to reduced capacitor area.",

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AU - Tamtrakarn, Atit

AU - Sakurai, Takayasu

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AB - An outside-rail output opamp targeting for future scaled MOSFETs is designed and the 3-V-output operation is successfully verified using 1.8-V standard CMOS process. This is the first experimental verification of an outside-rail opamp design which shows area advantage over un-scaled and insiderail design while keeping signal-to-noise ratio and gain bandwidth constant. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8V 0.18-μm standard CMOS process. The chip area is estimated to be 47% of the conventional opamp using a 0.35-μm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-mμ CMOS design due to reduced capacitor area.

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An outside-rail opamp design targeting for future scaled transistors

Abstract

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