An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems

Peter Toth, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work presents a novel control loop concept to adjust dynamically a differential ring oscillators (DRO) biasing in order to improve the phase noise performance (PN) in the ultra-low-power domain. Applying this proposed feedback system on any DRO with a tail current source is possible. The following paper presents the proposed concept and includes measurements of a 180 nm CMOS integrated prototype system, which underlines the feasibility of the discussed idea. Measurements show an up to 35 dBc/Hz phase noise improvement with an active control loop. Moreover, the tuning range of the implemented ring oscillator is extended by about 430 % compared to fixed bias operation. These values are measured at a minimum oscillation power consumption of 55 pW/Hz. University LSI Design Contest ASP-DAC 2021

Original languageEnglish
Title of host publicationProceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages9-10
Number of pages2
ISBN (Electronic)9781450379991
DOIs
Publication statusPublished - 2021 Jan 18
Event26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 - Virtual, Online, Japan
Duration: 2021 Jan 182021 Jan 21

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
CountryJapan
CityVirtual, Online
Period21/1/1821/1/21

Keywords

  • amplitude feedback loop
  • phase-noise improving
  • time-mode circuit

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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