Analysis and design of an 8.5-Gb/s/Link multi-drop bus using energy-equipartitioned transmission line couplers

Atsutake Kosuge, Shu Ishizuka, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

An 8.5-Gb/s/link non-contact multi-drop bus is presented. The signal reflections that limit the data rates of conventional multi-drop bus interfaces are dramatically reduced by using transmission line couplers at each signal branching point. As an energy-equipartitioned technique provides the same signal level to every port, wider receiver margin is achieved. The data rate is improved by 1.8 times compared to the most advanced multi-drop bus interface. The theoretical analysis and design techniques of energy-equipartitioned transmission line couplers are discussed in this paper. The design methodologies were verified through simulations performed by using a full-3D EM-simulator and experiments with FR4 test boards. Due to the low-cut characteristics of the couplers, the low-frequency components are cut off so that differentiated pulses arrive at the receiver input point. A receiver detects and recovers the received pulses by integrating them using hysteresis characteristics. The design techniques of the transceiver for the transmission line couplers are also discussed in this paper. The proposed methods were verified by using a test chip fabricated with a 90-nm CMOS process. Experiments with a prototype of an eight-drop multi-drop bus system confirmed BER < 10-14 at a data rate of 8.5-Gb/s/link. The measured timing margin at the far-end module was 0.49-UI at a BER of 10-12. The power consumption of the transceiver was 75.6-mW at a supply voltage of 1.2-V.

Original languageEnglish
Article number7161411
Pages (from-to)2122-2131
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume62
Issue number8
DOIs
Publication statusPublished - 2015 Aug 1

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Electric lines
Transceivers
Hysteresis
Electric power utilization
Simulators
Experiments
Electric potential

Keywords

  • DRAM interface
  • multi-drop bus
  • transceiver
  • transmission line coupler

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Analysis and design of an 8.5-Gb/s/Link multi-drop bus using energy-equipartitioned transmission line couplers. / Kosuge, Atsutake; Ishizuka, Shu; Taguchi, Masao; Ishikuro, Hiroki; Kuroda, Tadahiro.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, No. 8, 7161411, 01.08.2015, p. 2122-2131.

Research output: Contribution to journalArticle

@article{4abdf3a876ee4c2aac4ca224eae70b8d,
title = "Analysis and design of an 8.5-Gb/s/Link multi-drop bus using energy-equipartitioned transmission line couplers",
abstract = "An 8.5-Gb/s/link non-contact multi-drop bus is presented. The signal reflections that limit the data rates of conventional multi-drop bus interfaces are dramatically reduced by using transmission line couplers at each signal branching point. As an energy-equipartitioned technique provides the same signal level to every port, wider receiver margin is achieved. The data rate is improved by 1.8 times compared to the most advanced multi-drop bus interface. The theoretical analysis and design techniques of energy-equipartitioned transmission line couplers are discussed in this paper. The design methodologies were verified through simulations performed by using a full-3D EM-simulator and experiments with FR4 test boards. Due to the low-cut characteristics of the couplers, the low-frequency components are cut off so that differentiated pulses arrive at the receiver input point. A receiver detects and recovers the received pulses by integrating them using hysteresis characteristics. The design techniques of the transceiver for the transmission line couplers are also discussed in this paper. The proposed methods were verified by using a test chip fabricated with a 90-nm CMOS process. Experiments with a prototype of an eight-drop multi-drop bus system confirmed BER < 10-14 at a data rate of 8.5-Gb/s/link. The measured timing margin at the far-end module was 0.49-UI at a BER of 10-12. The power consumption of the transceiver was 75.6-mW at a supply voltage of 1.2-V.",
keywords = "DRAM interface, multi-drop bus, transceiver, transmission line coupler",
author = "Atsutake Kosuge and Shu Ishizuka and Masao Taguchi and Hiroki Ishikuro and Tadahiro Kuroda",
year = "2015",
month = "8",
day = "1",
doi = "10.1109/TCSI.2015.2437515",
language = "English",
volume = "62",
pages = "2122--2131",
journal = "IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

TY - JOUR

T1 - Analysis and design of an 8.5-Gb/s/Link multi-drop bus using energy-equipartitioned transmission line couplers

AU - Kosuge, Atsutake

AU - Ishizuka, Shu

AU - Taguchi, Masao

AU - Ishikuro, Hiroki

AU - Kuroda, Tadahiro

PY - 2015/8/1

Y1 - 2015/8/1

N2 - An 8.5-Gb/s/link non-contact multi-drop bus is presented. The signal reflections that limit the data rates of conventional multi-drop bus interfaces are dramatically reduced by using transmission line couplers at each signal branching point. As an energy-equipartitioned technique provides the same signal level to every port, wider receiver margin is achieved. The data rate is improved by 1.8 times compared to the most advanced multi-drop bus interface. The theoretical analysis and design techniques of energy-equipartitioned transmission line couplers are discussed in this paper. The design methodologies were verified through simulations performed by using a full-3D EM-simulator and experiments with FR4 test boards. Due to the low-cut characteristics of the couplers, the low-frequency components are cut off so that differentiated pulses arrive at the receiver input point. A receiver detects and recovers the received pulses by integrating them using hysteresis characteristics. The design techniques of the transceiver for the transmission line couplers are also discussed in this paper. The proposed methods were verified by using a test chip fabricated with a 90-nm CMOS process. Experiments with a prototype of an eight-drop multi-drop bus system confirmed BER < 10-14 at a data rate of 8.5-Gb/s/link. The measured timing margin at the far-end module was 0.49-UI at a BER of 10-12. The power consumption of the transceiver was 75.6-mW at a supply voltage of 1.2-V.

AB - An 8.5-Gb/s/link non-contact multi-drop bus is presented. The signal reflections that limit the data rates of conventional multi-drop bus interfaces are dramatically reduced by using transmission line couplers at each signal branching point. As an energy-equipartitioned technique provides the same signal level to every port, wider receiver margin is achieved. The data rate is improved by 1.8 times compared to the most advanced multi-drop bus interface. The theoretical analysis and design techniques of energy-equipartitioned transmission line couplers are discussed in this paper. The design methodologies were verified through simulations performed by using a full-3D EM-simulator and experiments with FR4 test boards. Due to the low-cut characteristics of the couplers, the low-frequency components are cut off so that differentiated pulses arrive at the receiver input point. A receiver detects and recovers the received pulses by integrating them using hysteresis characteristics. The design techniques of the transceiver for the transmission line couplers are also discussed in this paper. The proposed methods were verified by using a test chip fabricated with a 90-nm CMOS process. Experiments with a prototype of an eight-drop multi-drop bus system confirmed BER < 10-14 at a data rate of 8.5-Gb/s/link. The measured timing margin at the far-end module was 0.49-UI at a BER of 10-12. The power consumption of the transceiver was 75.6-mW at a supply voltage of 1.2-V.

KW - DRAM interface

KW - multi-drop bus

KW - transceiver

KW - transmission line coupler

UR - http://www.scopus.com/inward/record.url?scp=85027952151&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85027952151&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2015.2437515

DO - 10.1109/TCSI.2015.2437515

M3 - Article

AN - SCOPUS:85027952151

VL - 62

SP - 2122

EP - 2131

JO - IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

JF - IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

SN - 1549-8328

IS - 8

M1 - 7161411

ER -