Analysis and design of transceiver circuit and inductor layout for inductive inter-chip wireless superconnect

Noriyuki Miura; Daisuke Mizoguchi; Yusmeeraz Binti Yusof; Takayasu Sakurai; Tadahiro Kuroda

Analysis and design of transceiver circuit and inductor layout for inductive inter-chip wireless superconnect

Noriyuki Miura, Daisuke Mizoguchi, Yusmeeraz Binti Yusof, Takayasu Sakurai, Tadahiro Kuroda

Research output: Contribution to conference › Paper › peer-review

Abstract

A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by an equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communications distance, transmit power, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive Non-Return-to-Zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35μm CMOS. Accuracy of the models is verified. Bit error rate is investigated for various inductor layouts and communications distance. The maximum data rate is 1.25Gb/s/channel. Power dissipation is 43mW in the transmitter and 2.6mW in the receiver at 3.3V. If chip thickness is reduced to 30μm in 90nm device generation, power dissipation will be ImW/channel or bandwidth will be ITb/s/mm².

Original language	English
Pages	246-249
Number of pages	4
Publication status	Published - 2004 Sept 29
Event	2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States Duration: 2004 Jun 17 → 2004 Jun 19

Other

Other	2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
Country/Territory	United States
City	Honolulu, HI
Period	04/6/17 → 04/6/19

Keywords

High bandwidth
Inductor
Low power
SiP
Wireless bus

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Analysis and design of transceiver circuit and inductor layout for inductive inter-chip wireless superconnect. / Miura, Noriyuki; Mizoguchi, Daisuke; Yusof, Yusmeeraz Binti et al.
2004. 246-249 Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States.

Research output: Contribution to conference › Paper › peer-review

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title = "Analysis and design of transceiver circuit and inductor layout for inductive inter-chip wireless superconnect",

abstract = "A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by an equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communications distance, transmit power, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive Non-Return-to-Zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35μm CMOS. Accuracy of the models is verified. Bit error rate is investigated for various inductor layouts and communications distance. The maximum data rate is 1.25Gb/s/channel. Power dissipation is 43mW in the transmitter and 2.6mW in the receiver at 3.3V. If chip thickness is reduced to 30μm in 90nm device generation, power dissipation will be ImW/channel or bandwidth will be ITb/s/mm2.",

keywords = "High bandwidth, Inductor, Low power, SiP, Wireless bus",

author = "Noriyuki Miura and Daisuke Mizoguchi and Yusof, {Yusmeeraz Binti} and Takayasu Sakurai and Tadahiro Kuroda",

year = "2004",

month = sep,

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AU - Miura, Noriyuki

AU - Mizoguchi, Daisuke

AU - Yusof, Yusmeeraz Binti

AU - Sakurai, Takayasu

AU - Kuroda, Tadahiro

PY - 2004/9/29

Y1 - 2004/9/29

N2 - A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by an equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communications distance, transmit power, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive Non-Return-to-Zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35μm CMOS. Accuracy of the models is verified. Bit error rate is investigated for various inductor layouts and communications distance. The maximum data rate is 1.25Gb/s/channel. Power dissipation is 43mW in the transmitter and 2.6mW in the receiver at 3.3V. If chip thickness is reduced to 30μm in 90nm device generation, power dissipation will be ImW/channel or bandwidth will be ITb/s/mm2.

AB - A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by an equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communications distance, transmit power, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive Non-Return-to-Zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35μm CMOS. Accuracy of the models is verified. Bit error rate is investigated for various inductor layouts and communications distance. The maximum data rate is 1.25Gb/s/channel. Power dissipation is 43mW in the transmitter and 2.6mW in the receiver at 3.3V. If chip thickness is reduced to 30μm in 90nm device generation, power dissipation will be ImW/channel or bandwidth will be ITb/s/mm2.

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KW - Inductor

KW - Low power

KW - SiP

KW - Wireless bus

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ER -

Analysis and design of transceiver circuit and inductor layout for inductive inter-chip wireless superconnect

Abstract

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Keywords

ASJC Scopus subject areas

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