Analysis and optimization of BiCMOS gate circuits

Tadahiro Kuroda, Yoshinori Sakata, Kenji Matsuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

An optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed whose parameters can be extracted with SPICE simulations. Therefore a device model can be precise, while keeping the optimization procedure simple and unchangeable in any device generation. With the proposed procedure, BiCMOS gate delays can be calculated quickly and optimized efficiently just by looking up design tables that are obtained easily and are applicable to any design with the same device technology. The sizing strategy of cascaded drivers is also studied. BiCMOS-BiCMOS cascaded buffers are optimized when the scale-up factor is e2.3, while BiCMOS-CMOS cascaded buffers become the fastest when the scale-up factor, e1.6, is employed. The strategy was successfully applied to the design of high-speed BiCMOS static-RAM (SRAM) macros for standard cell libraries.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages2112-2115
Number of pages4
Volume4
Publication statusPublished - 1991
Externally publishedYes
Event1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore
Duration: 1991 Jun 111991 Jun 14

Other

Other1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5)
CitySingapore, Singapore
Period91/6/1191/6/14

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kuroda, T., Sakata, Y., & Matsuo, K. (1991). Analysis and optimization of BiCMOS gate circuits. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 4, pp. 2112-2115). Publ by IEEE.