Analysis and techniques for mitigating interference from power/signal lines and to SRAM circuits in CMOS inductive-coupling link for low-power 3-D system integration

Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)

Abstract

This paper discusses analysis and techniques for mitigating interference of an inductive-coupling inter-chip link. Electromagnetic interference from power/signal lines and to SRAM circuits was simulated and measured. In order to verify the interference, test chips were designed and fabricated using 65-nm CMOS technology. The measurement results revealed that: 1) interference from power lines depends on the shape of the power lines; 2) interference from signal lines can be canceled by increasing transmitter power by only 9%; and 3) interference with SRAM circuits is less important than other issues under ordinary conditions. Based on the measurement results, interference mitigation techniques are proposed and investigated.

Original languageEnglish
Article number5545493
Pages (from-to)1902-1907
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume19
Issue number10
DOIs
Publication statusPublished - 2011 Oct

Keywords

  • CMOS integrated circuits
  • SiP
  • high-speed interconnect
  • low-power design
  • wireless interconnect

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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