Analysis of inductive coupling and design of rectifier circuit for inter-chipwireless power link

Yuxiang Yuan, Yoichi Yoshid, Tadahiro Kuroda

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the highfrequency performance of the rectifier block. Test chips are fabricated in a 0.18 μm CMOS process. With a pair of 700 × 700 μm2 on-chip inductors, the test chips achieve 10% peak efficiency and 36mW power transmission. Compared with the previous work the received power is 13 times larger for the same inductor size [7].

Original languageEnglish
Pages (from-to)164-171
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE93-C
Issue number2
DOIs
Publication statusPublished - 2010

Fingerprint

Power transmission
Telecommunication links
Networks (circuits)
Leakage currents
Equivalent circuits
Substrates

Keywords

  • Inductivecoupling
  • Inductor
  • Rectifier
  • SiP
  • Wireless power delivery
  • Wireless power link

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Analysis of inductive coupling and design of rectifier circuit for inter-chipwireless power link. / Yuan, Yuxiang; Yoshid, Yoichi; Kuroda, Tadahiro.

In: IEICE Transactions on Electronics, Vol. E93-C, No. 2, 2010, p. 164-171.

Research output: Contribution to journalArticle

@article{ab881fe46d4c4e7fbaf627e75744799a,
title = "Analysis of inductive coupling and design of rectifier circuit for inter-chipwireless power link",
abstract = "A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the highfrequency performance of the rectifier block. Test chips are fabricated in a 0.18 μm CMOS process. With a pair of 700 × 700 μm2 on-chip inductors, the test chips achieve 10{\%} peak efficiency and 36mW power transmission. Compared with the previous work the received power is 13 times larger for the same inductor size [7].",
keywords = "Inductivecoupling, Inductor, Rectifier, SiP, Wireless power delivery, Wireless power link",
author = "Yuxiang Yuan and Yoichi Yoshid and Tadahiro Kuroda",
year = "2010",
doi = "10.1587/transele.E93.C.164",
language = "English",
volume = "E93-C",
pages = "164--171",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "2",

}

TY - JOUR

T1 - Analysis of inductive coupling and design of rectifier circuit for inter-chipwireless power link

AU - Yuan, Yuxiang

AU - Yoshid, Yoichi

AU - Kuroda, Tadahiro

PY - 2010

Y1 - 2010

N2 - A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the highfrequency performance of the rectifier block. Test chips are fabricated in a 0.18 μm CMOS process. With a pair of 700 × 700 μm2 on-chip inductors, the test chips achieve 10% peak efficiency and 36mW power transmission. Compared with the previous work the received power is 13 times larger for the same inductor size [7].

AB - A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the highfrequency performance of the rectifier block. Test chips are fabricated in a 0.18 μm CMOS process. With a pair of 700 × 700 μm2 on-chip inductors, the test chips achieve 10% peak efficiency and 36mW power transmission. Compared with the previous work the received power is 13 times larger for the same inductor size [7].

KW - Inductivecoupling

KW - Inductor

KW - Rectifier

KW - SiP

KW - Wireless power delivery

KW - Wireless power link

UR - http://www.scopus.com/inward/record.url?scp=77950402428&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77950402428&partnerID=8YFLogxK

U2 - 10.1587/transele.E93.C.164

DO - 10.1587/transele.E93.C.164

M3 - Article

AN - SCOPUS:77950402428

VL - E93-C

SP - 164

EP - 171

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 2

ER -