The building block computing system can build several systems by stacking small chips with inductive coupling wireless chip-to-chip connection TCI (Through Chip Interface). TCI IP (Intellectual Property) was developed by using the Renesas 65nm SOTB process, and several family chips have been developed with the IP. Although all of the chips worked alone without problems, when they were stacked to construct a system, problems were found on some combinations of chips that TCI did not work as designed. This paper analyzes the resistances of power grid of chips with IPs from their layout to investigate the reason of the problems. Then, the voltage drop is estimated with the model built from the real chip evaluation. The analysis results appeared that in some chips, the resistances of the power grid are more than double of the target value, and because of the voltage drop, the supply voltage given to the IP of the largest chip SMTT is about the half of given to the power pad. Although it comes from the limitation of the I/O pads for chip stacking and fixed location of TCI IPs, we must take special care of the design of the transmitter power grid.