TY - GEN
T1 - Architecture and compiler co-optimization for high performance computing
AU - Nakamura, H.
AU - Kondo, M.
AU - Ohneda, T.
AU - Fujita, M.
AU - Chiba, S.
AU - Sato, M.
AU - Boku, T.
N1 - Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - The performance gap between processor and memory is very serious problem in high-performance computing because effective performance is limited by memory ability. In order to overcome this problem, it is indispensable to make good use of wide on-chip memory bandwidth. For this purpose, architecture and compiler co-optimization is a promising approach because most data access is regular and/or predictable in high performance computing. Thus, we propose a new VLSI architecture called SCIMA as a platform of the co-optimization. SCIMA integrates software controllable memory (SCM) into a processor chip in addition to ordinary data cache. SCM and cache can be reconfigured by software during computation. Hence, the memory hierarchy itself is the target of compiler optimization. In this sense, architecture and compiler co-optimization is realized in SCIMA. Towards the co-optimization, we have developed a directive-based compiler and an algorithm of SCM usage to insert directives automatically. In this paper, we present the directives and the outline of the algorithm for automatic optimization.
AB - The performance gap between processor and memory is very serious problem in high-performance computing because effective performance is limited by memory ability. In order to overcome this problem, it is indispensable to make good use of wide on-chip memory bandwidth. For this purpose, architecture and compiler co-optimization is a promising approach because most data access is regular and/or predictable in high performance computing. Thus, we propose a new VLSI architecture called SCIMA as a platform of the co-optimization. SCIMA integrates software controllable memory (SCM) into a processor chip in addition to ordinary data cache. SCM and cache can be reconfigured by software during computation. Hence, the memory hierarchy itself is the target of compiler optimization. In this sense, architecture and compiler co-optimization is realized in SCIMA. Towards the co-optimization, we have developed a directive-based compiler and an algorithm of SCM usage to insert directives automatically. In this paper, we present the directives and the outline of the algorithm for automatic optimization.
KW - Bandwidth
KW - Computer architecture
KW - Delay
KW - Electronic mail
KW - Hardware
KW - High performance computing
KW - Optimizing compilers
KW - Prefetching
KW - Throughput
KW - Very large scale integration
UR - http://www.scopus.com/inward/record.url?scp=4544223229&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=4544223229&partnerID=8YFLogxK
U2 - 10.1109/IWIA.2002.1035018
DO - 10.1109/IWIA.2002.1035018
M3 - Conference contribution
AN - SCOPUS:4544223229
T3 - Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
SP - 50
EP - 56
BT - International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002
A2 - Joe, Kazuki
A2 - Veidenbaum, Alex
PB - IEEE Computer Society
T2 - International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002
Y2 - 11 January 2002
ER -