Architecture and compiler co-optimization for high performance computing

H. Nakamura, M. Kondo, T. Ohneda, M. Fujita, S. Chiba, M. Sato, T. Boku

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

The performance gap between processor and memory is very serious problem in high-performance computing because effective performance is limited by memory ability. In order to overcome this problem, it is indispensable to make good use of wide on-chip memory bandwidth. For this purpose, architecture and compiler co-optimization is a promising approach because most data access is regular and/or predictable in high performance computing. Thus, we propose a new VLSI architecture called SCIMA as a platform of the co-optimization. SCIMA integrates software controllable memory (SCM) into a processor chip in addition to ordinary data cache. SCM and cache can be reconfigured by software during computation. Hence, the memory hierarchy itself is the target of compiler optimization. In this sense, architecture and compiler co-optimization is realized in SCIMA. Towards the co-optimization, we have developed a directive-based compiler and an algorithm of SCM usage to insert directives automatically. In this paper, we present the directives and the outline of the algorithm for automatic optimization.

Original languageEnglish
Title of host publicationInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002
EditorsKazuki Joe, Alex Veidenbaum
PublisherIEEE Computer Society
Pages50-56
Number of pages7
ISBN (Electronic)0769516351
DOIs
Publication statusPublished - 2002
Externally publishedYes
EventInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002 - Big Island, United States
Duration: 2002 Jan 11 → …

Publication series

NameProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
Volume2002-January
ISSN (Print)1537-3223

Other

OtherInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002
Country/TerritoryUnited States
CityBig Island
Period02/1/11 → …

Keywords

  • Bandwidth
  • Computer architecture
  • Delay
  • Electronic mail
  • Hardware
  • High performance computing
  • Optimizing compilers
  • Prefetching
  • Throughput
  • Very large scale integration

ASJC Scopus subject areas

  • Hardware and Architecture

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