Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing

Hiroaki Nishi, Shinji Nishimura, Katsuyoshi Harasawa, Tomohiro Kudoh, Hideharu Amano

Research output: Contribution to journalArticlepeer-review

Abstract

RHiNET-3/SW is the third-generation switch used in the RHiNET-3 system. It provides both low-latency processing and flexible connection due to its use of a credit-based flow-control mechanism, topology-free routing, and deadlock-free routing. The aggregate throughput of RHiNET-3/SW is 80 Gbps, and the latency is 140 ns. RHiNET-3/SW also provides a hop-by-hop retransmission mechanism. Simulation demonstrated that the effective throughput at a node in a 64-node torus RHiNET-3 system is equivalent to the effective throughput of a 64-bit 33-MHz PCI bus and that the performance of RHiNET-3/SW almost equals or exceeds the best performance of RHiNET-2/SW, the second-generation switch. Although credit-based flow control requires 26% more gates than rate-based flow control to manage the virtual channels (VCs), it requires less VC memory than rate-based flow control. Moreover, its use in a network system reduces latency and increases the maximum throughput compared to rate-based flow control.

Original languageEnglish
Pages (from-to)1987-1995
Number of pages9
JournalIEICE Transactions on Information and Systems
VolumeE86-D
Issue number10
Publication statusPublished - 2003 Oct

Keywords

  • Cluster computing network
  • Flow control
  • High-performance system
  • RHiNET

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

Fingerprint Dive into the research topics of 'Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing'. Together they form a unique fingerprint.

Cite this