Architecture design of versatile recognition processor for sensornet applications

Yuichi Hori, Yuya Hanai, Jun Nishimura, Tadahiro Kuroda

    Research output: Contribution to journalArticle

    2 Citations (Scopus)

    Abstract

    This article presents the multiobject parallel recognition architecture of a versatile recognition processor (VRP) that detects and recognizes objects from images, videos, sounds, and acceleration signals. It offers eight times better power efficiency than conventional object recognition processors, making it ideal for mobile application platforms and wireless sensor network systems.

    Original languageEnglish
    Article number5372155
    Pages (from-to)44-57
    Number of pages14
    JournalIEEE Micro
    Volume29
    Issue number6
    DOIs
    Publication statusPublished - 2009 Nov 1

    Keywords

    • AdaBoost
    • Haar-like feature
    • Low power
    • Real time
    • Recognition
    • Wireless sensor network

    ASJC Scopus subject areas

    • Software
    • Hardware and Architecture
    • Electrical and Electronic Engineering

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  • Cite this

    Hori, Y., Hanai, Y., Nishimura, J., & Kuroda, T. (2009). Architecture design of versatile recognition processor for sensornet applications. IEEE Micro, 29(6), 44-57. [5372155]. https://doi.org/10.1109/MM.2009.93