TY - GEN
T1 - Attempt-1
T2 - 6th International Workshop on Field-Programmable Logic and Applications, FPL 1996
AU - Inoue, Keisuke
AU - Kisuki, Tohru
AU - Okuno, Michitaka
AU - Shimizu, Etsuko
AU - Terasawa, Takuya
AU - Amano, Hideharu
N1 - Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 1996.
PY - 1996
Y1 - 1996
N2 - The future advanced technologies of devices will enable to implement some number of processors into a single chip. We call such a chip the multiprocessor-chip. In such a multiprocessor-chip, architectural trade-off is completely different from current bus connected multiprocessors. In order to emulate such future multiprocessors, a reconfigurable testbed multiprocessor ATTEMPT-1 is proposed. By using programmable devices (CPLDs and FPGAs) in the core of the system, various parameters of the cache and bus system are selectable. Since the each core of controller is described in the HDL (Hardware Description Language) and implemented on CPLD, cache protocols and bus protocols can be changed just by rewriting description on the state transitions. By using high speed FPGAs in the data path, enough high speed (25MHz clock) is kept in spite of its flexibilty.
AB - The future advanced technologies of devices will enable to implement some number of processors into a single chip. We call such a chip the multiprocessor-chip. In such a multiprocessor-chip, architectural trade-off is completely different from current bus connected multiprocessors. In order to emulate such future multiprocessors, a reconfigurable testbed multiprocessor ATTEMPT-1 is proposed. By using programmable devices (CPLDs and FPGAs) in the core of the system, various parameters of the cache and bus system are selectable. Since the each core of controller is described in the HDL (Hardware Description Language) and implemented on CPLD, cache protocols and bus protocols can be changed just by rewriting description on the state transitions. By using high speed FPGAs in the data path, enough high speed (25MHz clock) is kept in spite of its flexibilty.
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U2 - 10.1007/3-540-61730-2_21
DO - 10.1007/3-540-61730-2_21
M3 - Conference contribution
AN - SCOPUS:84955580709
SN - 9783540617303
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 200
EP - 209
BT - Field-Programmable Logic
A2 - Hartenstein, Reiner W.
A2 - Glesner, Manfred
PB - Springer Verlag
Y2 - 23 September 1996 through 25 September 1996
ER -