AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Various parallel applications, such as numerical convergent computation and multimedia processing, have intrinsic tolerance to inaccuracies that allow soft errors, i.e. bit flips, on a chip. However, existing Network-on-Chips (NoCs) guarantee error-free data transfer; thus, encountering limits to reduce the power consumption. In this context, we propose an approximate dual-voltage NoC, called AxNoC. An AxNoC router uses a per-flit look-ahead power management so that headers and important-data flits are perfectly transferred at a high voltage while the remaining flits may incur bit flips by decreasing the supply voltage. An AxNoC router isolates the critical path when the supply voltage is low since such a critical path is enabled only at high voltage. The critical path isolation enables low-voltage operation to work at the same operating frequency at high voltage. An AxNoC router was implemented using a 28nm process and the evaluation results illustrate its efficiency to reduce the power consumption reaching up to 43% while incurring a small area overhead that does not exceed 6.2%. We also demonstrate that AxNoC exhibits an acceptable accuracy illustrated in a sufficiently small geomean of error.

Original languageEnglish
Title of host publication2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538648933
DOIs
Publication statusPublished - 2018 Oct 26
Event12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018 - Torino, Italy
Duration: 2018 Oct 42018 Oct 5

Other

Other12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018
CountryItaly
CityTorino
Period18/10/418/10/5

Fingerprint

Electric potential
Routers
Electric power utilization
Data transfer
Network-on-chip
Processing

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Ahmed, A. B., Fujiki, D., Matsutani, H., Koibuchi, M., & Amano, H. (2018). AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. In 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018 [8512158] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NOCS.2018.8512158

AxNoC : Low-power Approximate Network-on-Chips using Critical-Path Isolation. / Ahmed, Akram Ben; Fujiki, Daichi; Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu.

2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. 8512158.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ahmed, AB, Fujiki, D, Matsutani, H, Koibuchi, M & Amano, H 2018, AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. in 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018., 8512158, Institute of Electrical and Electronics Engineers Inc., 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018, Torino, Italy, 18/10/4. https://doi.org/10.1109/NOCS.2018.8512158
Ahmed AB, Fujiki D, Matsutani H, Koibuchi M, Amano H. AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. In 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018. Institute of Electrical and Electronics Engineers Inc. 2018. 8512158 https://doi.org/10.1109/NOCS.2018.8512158
Ahmed, Akram Ben ; Fujiki, Daichi ; Matsutani, Hiroki ; Koibuchi, Michihiro ; Amano, Hideharu. / AxNoC : Low-power Approximate Network-on-Chips using Critical-Path Isolation. 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018. Institute of Electrical and Electronics Engineers Inc., 2018.
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