Balanced dimension-order routing for k-ary n-cubes

Jose Miguel Montañana, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Current Network-on-Chip (NoC) architectures sometimes employ mesh or torus topology with the dimensionorder routing. In this paper, we propose a deadlock-free routing algorithm, referred to as Balanced Dimension-Order Routing (BDOR), which provides the balanced minimal paths to each destination based on the simple routing regulations. Since the BDOR has the similar path regularity to that of the dimensionorder routing, its implementation can be lightweight, and most of its modules can be borrowed from the router for the dimension-order routing. Evaluation results show that the BDOR router increases by 3.4% hardware amount compared with the router for the dimension-order routing. Also show that the throughput of the BDOR outperforms on average up to 14% that of the dimension-order routing on two-dimensional mesh and torus.

Original languageEnglish
Title of host publicationICPPW 2009 - The 38th International Conference Parallel Processing Workshops
Pages499-506
Number of pages8
DOIs
Publication statusPublished - 2009 Dec 1
Event38th International Conference Parallel Processing Workshops, ICPPW 2009 - Vienna, Austria
Duration: 2009 Sep 222009 Sep 25

Publication series

NameProceedings of the International Conference on Parallel Processing Workshops
ISSN (Print)1530-2016

Other

Other38th International Conference Parallel Processing Workshops, ICPPW 2009
CountryAustria
CityVienna
Period09/9/2209/9/25

ASJC Scopus subject areas

  • Software
  • Mathematics(all)
  • Hardware and Architecture

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  • Cite this

    Montañana, J. M., Koibuchi, M., Matsutani, H., & Amano, H. (2009). Balanced dimension-order routing for k-ary n-cubes. In ICPPW 2009 - The 38th International Conference Parallel Processing Workshops (pp. 499-506). [5365405] (Proceedings of the International Conference on Parallel Processing Workshops). https://doi.org/10.1109/ICPPW.2009.64