Abstract
The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low Vth and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. Vth can be lowered to 0.23 VDD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V VDD compared with the case where this scheme is not applied.
| Original language | English |
|---|---|
| Pages | 70-71 |
| Number of pages | 2 |
| Publication status | Published - 2000 Jan 1 |
| Externally published | Yes |
| Event | 2000 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 2000 Jun 15 → 2000 Jun 17 |
Other
| Other | 2000 Symposium on VLSI Circuits |
|---|---|
| City | Honolulu, HI, USA |
| Period | 00/6/15 → 00/6/17 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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Cite this
Agawa, K., Hara, H., Takayanagi, T., & Kuroda, T. (2000). Bit-line leakage compensation scheme for low-voltage SRAM's. 70-71. Paper presented at 2000 Symposium on VLSI Circuits, Honolulu, HI, USA, .