Abstract
The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low Vth and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. Vth can be lowered to 0.23 VDD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V VDD compared with the case where this scheme is not applied.
| Original language | English |
|---|---|
| Title of host publication | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
| Publisher | IEEE |
| Pages | 70-71 |
| Number of pages | 2 |
| Publication status | Published - 2000 |
| Externally published | Yes |
| Event | 2000 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 2000 Jun 15 → 2000 Jun 17 |
Other
| Other | 2000 Symposium on VLSI Circuits |
|---|---|
| City | Honolulu, HI, USA |
| Period | 00/6/15 → 00/6/17 |
Fingerprint
ASJC Scopus subject areas
- Engineering(all)
Cite this
Bit-line leakage compensation scheme for low-voltage SRAM's. / Agawa, Ken'ichi; Hara, Hiroyuki; Takayanagi, Toshinari; Kuroda, Tadahiro.
IEEE Symposium on VLSI Circuits, Digest of Technical Papers. IEEE, 2000. p. 70-71.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Bit-line leakage compensation scheme for low-voltage SRAM's
AU - Agawa, Ken'ichi
AU - Hara, Hiroyuki
AU - Takayanagi, Toshinari
AU - Kuroda, Tadahiro
PY - 2000
Y1 - 2000
N2 - The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low Vth and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. Vth can be lowered to 0.23 VDD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V VDD compared with the case where this scheme is not applied.
AB - The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low Vth and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. Vth can be lowered to 0.23 VDD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V VDD compared with the case where this scheme is not applied.
UR - http://www.scopus.com/inward/record.url?scp=0033683112&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0033683112&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0033683112
SP - 70
EP - 71
BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
PB - IEEE
ER -