Bit-line leakage compensation scheme for low-voltage SRAM's

Ken'ichi Agawa; Hiroyuki Hara; Toshinari Takayanagi; Tadahiro Kuroda

Bit-line leakage compensation scheme for low-voltage SRAM's

Ken'ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda

Research output: Contribution to conference › Paper › peer-review

Abstract

The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low V_th and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. V_th can be lowered to 0.23 V_DD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V V_DD compared with the case where this scheme is not applied.

Original language	English
Pages	70-71
Number of pages	2
Publication status	Published - 2000 Jan 1
Externally published	Yes
Event	2000 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 2000 Jun 15 → 2000 Jun 17

Other

Other	2000 Symposium on VLSI Circuits
City	Honolulu, HI, USA
Period	00/6/15 → 00/6/17

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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@conference{7f045809a1ac454d81796a47978f461c,

title = "Bit-line leakage compensation scheme for low-voltage SRAM's",

abstract = "The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low Vth and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. Vth can be lowered to 0.23 VDD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V VDD compared with the case where this scheme is not applied.",

author = "Ken'ichi Agawa and Hiroyuki Hara and Toshinari Takayanagi and Tadahiro Kuroda",

year = "2000",

month = jan,

day = "1",

language = "English",

pages = "70--71",

note = "2000 Symposium on VLSI Circuits ; Conference date: 15-06-2000 Through 17-06-2000",

}

TY - CONF

T1 - Bit-line leakage compensation scheme for low-voltage SRAM's

AU - Agawa, Ken'ichi

AU - Hara, Hiroyuki

AU - Takayanagi, Toshinari

AU - Kuroda, Tadahiro

PY - 2000/1/1

Y1 - 2000/1/1

N2 - The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low Vth and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. Vth can be lowered to 0.23 VDD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V VDD compared with the case where this scheme is not applied.

AB - The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low Vth and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. Vth can be lowered to 0.23 VDD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V VDD compared with the case where this scheme is not applied.

UR - http://www.scopus.com/inward/record.url?scp=0033683112&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033683112&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0033683112

SP - 70

EP - 71

T2 - 2000 Symposium on VLSI Circuits

Y2 - 15 June 2000 through 17 June 2000

ER -