Bit-line leakage compensation scheme for low-voltage SRAM's

Ken'ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low Vth and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. Vth can be lowered to 0.23 VDD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V VDD compared with the case where this scheme is not applied.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
PublisherIEEE
Pages70-71
Number of pages2
Publication statusPublished - 2000
Externally publishedYes
Event2000 Symposium on VLSI Circuits - Honolulu, HI, USA
Duration: 2000 Jun 152000 Jun 17

Other

Other2000 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period00/6/1500/6/17

Fingerprint

Data storage equipment
Electric potential
Leakage currents
Transistors
Compensation and Redress

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Agawa, K., Hara, H., Takayanagi, T., & Kuroda, T. (2000). Bit-line leakage compensation scheme for low-voltage SRAM's. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 70-71). IEEE.

Bit-line leakage compensation scheme for low-voltage SRAM's. / Agawa, Ken'ichi; Hara, Hiroyuki; Takayanagi, Toshinari; Kuroda, Tadahiro.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. IEEE, 2000. p. 70-71.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Agawa, K, Hara, H, Takayanagi, T & Kuroda, T 2000, Bit-line leakage compensation scheme for low-voltage SRAM's. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers. IEEE, pp. 70-71, 2000 Symposium on VLSI Circuits, Honolulu, HI, USA, 00/6/15.
Agawa K, Hara H, Takayanagi T, Kuroda T. Bit-line leakage compensation scheme for low-voltage SRAM's. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. IEEE. 2000. p. 70-71
Agawa, Ken'ichi ; Hara, Hiroyuki ; Takayanagi, Toshinari ; Kuroda, Tadahiro. / Bit-line leakage compensation scheme for low-voltage SRAM's. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. IEEE, 2000. pp. 70-71
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