Bit-line leakage compensation scheme for low-voltage SRAM's

Ken'ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda

Research output: Contribution to conferencePaper

8 Citations (Scopus)

Abstract

The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low Vth and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. Vth can be lowered to 0.23 VDD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V VDD compared with the case where this scheme is not applied.

Original languageEnglish
Pages70-71
Number of pages2
Publication statusPublished - 2000 Jan 1
Externally publishedYes
Event2000 Symposium on VLSI Circuits - Honolulu, HI, USA
Duration: 2000 Jun 152000 Jun 17

Other

Other2000 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period00/6/1500/6/17

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Bit-line leakage compensation scheme for low-voltage SRAM's'. Together they form a unique fingerprint.

  • Cite this

    Agawa, K., Hara, H., Takayanagi, T., & Kuroda, T. (2000). Bit-line leakage compensation scheme for low-voltage SRAM's. 70-71. Paper presented at 2000 Symposium on VLSI Circuits, Honolulu, HI, USA, .