TY - GEN
T1 - BRein memory
T2 - 31st Symposium on VLSI Circuits, VLSI Circuits 2017
AU - Ando, Kota
AU - Ueyoshi, Kodai
AU - Orimo, Kentaro
AU - Yonekawa, Haruyoshi
AU - Sato, Shimpei
AU - Nakahara, Hiroki
AU - Ikebe, Masayuki
AU - Asai, Tetsuya
AU - Takamaeda-Yamazaki, Shinya
AU - Kuroda, Tadahiro
AU - Motomura, Masato
N1 - Funding Information:
This work was supported by JST ACCEL program. References [1] M. Courbariaux et al., arXiv:1602.02830, Mar. 2016. [2] M. Rastegari et al., arXiv:1603.05279, Aug. 2016. [3] L. Hou et al., arXiv:1611.01600, Nov. 2016. [4] F. Li et al., NIPS, 2016 (arXiv:1605.04711v2). [5] I. Hubara et al., arXiv:1609.07061, Sep. 2016. [6] H. Nakahara et al., FPGA, 2017, to be published. [7] E. Nurvitadhi et al., FPT, 2016, pp. 77-84. [8] H. Nakahara et al., FPT, 2016, pp. 273-276. [9] Y-H. Chen et al., ISSCC, 2016, pp. 262-263. [10] J. Sim et al., ISSCC, 2016, pp. 264-265. [11] B. Moons et al., VLSI Circuits, 2016, pp. 178-179.
Publisher Copyright:
© 2017 JSAP.
PY - 2017/8/10
Y1 - 2017/8/10
N2 - A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing architecture and stores varieties of binary/ternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip. The 0.6 W, 1.4 TOPS chip achieves performance and energy efficiency that is 10-102 and 102-104 times better than a CPU/GPU/FPGA.
AB - A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing architecture and stores varieties of binary/ternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip. The 0.6 W, 1.4 TOPS chip achieves performance and energy efficiency that is 10-102 and 102-104 times better than a CPU/GPU/FPGA.
UR - http://www.scopus.com/inward/record.url?scp=85034096665&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85034096665&partnerID=8YFLogxK
U2 - 10.23919/VLSIC.2017.8008533
DO - 10.23919/VLSIC.2017.8008533
M3 - Conference contribution
AN - SCOPUS:85034096665
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - C24-C25
BT - 2017 Symposium on VLSI Circuits, VLSI Circuits 2017
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 5 June 2017 through 8 June 2017
ER -