BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS

Kota Ando; Kodai Ueyoshi; Kentaro Orimo; Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Tadahiro Kuroda; Masato Motomura

doi:10.23919/VLSIC.2017.8008533

BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda, Masato Motomura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

49 Citations (Scopus)

Abstract

A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing architecture and stores varieties of binary/ternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip. The 0.6 W, 1.4 TOPS chip achieves performance and energy efficiency that is 10-10² and 10²-10⁴ times better than a CPU/GPU/FPGA.

Original language	English
Title of host publication	2017 Symposium on VLSI Circuits, VLSI Circuits 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C24-C25
ISBN (Electronic)	9784863486065
DOIs	https://doi.org/10.23919/VLSIC.2017.8008533
Publication status	Published - 2017 Aug 10
Event	31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan Duration: 2017 Jun 5 → 2017 Jun 8

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	31st Symposium on VLSI Circuits, VLSI Circuits 2017
Country/Territory	Japan
City	Kyoto
Period	17/6/5 → 17/6/8

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.23919/VLSIC.2017.8008533

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Ando, K., Ueyoshi, K., Orimo, K., Yonekawa, H., Sato, S., Nakahara, H., Ikebe, M., Asai, T., Takamaeda-Yamazaki, S., Kuroda, T., & Motomura, M. (2017). BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (pp. C24-C25). [8008533] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2017.8008533

BRein memory : A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS. / Ando, Kota; Ueyoshi, Kodai; Orimo, Kentaro; Yonekawa, Haruyoshi; Sato, Shimpei; Nakahara, Hiroki; Ikebe, Masayuki; Asai, Tetsuya; Takamaeda-Yamazaki, Shinya; Kuroda, Tadahiro; Motomura, Masato.

2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. C24-C25 8008533 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ando, K, Ueyoshi, K, Orimo, K, Yonekawa, H, Sato, S, Nakahara, H, Ikebe, M, Asai, T, Takamaeda-Yamazaki, S, Kuroda, T & Motomura, M 2017, BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS. in 2017 Symposium on VLSI Circuits, VLSI Circuits 2017., 8008533, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. C24-C25, 31st Symposium on VLSI Circuits, VLSI Circuits 2017, Kyoto, Japan, 17/6/5. https://doi.org/10.23919/VLSIC.2017.8008533

Ando K, Ueyoshi K, Orimo K, Yonekawa H, Sato S, Nakahara H et al. BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. C24-C25. 8008533. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.23919/VLSIC.2017.8008533

Ando, Kota ; Ueyoshi, Kodai ; Orimo, Kentaro ; Yonekawa, Haruyoshi ; Sato, Shimpei ; Nakahara, Hiroki ; Ikebe, Masayuki ; Asai, Tetsuya ; Takamaeda-Yamazaki, Shinya ; Kuroda, Tadahiro ; Motomura, Masato. / BRein memory : A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS. 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. C24-C25 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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abstract = "A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing architecture and stores varieties of binary/ternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip. The 0.6 W, 1.4 TOPS chip achieves performance and energy efficiency that is 10-102 and 102-104 times better than a CPU/GPU/FPGA.",

author = "Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Tadahiro Kuroda and Masato Motomura",

note = "Funding Information: This work was supported by JST ACCEL program. References [1]? M. Courbariaux et al., arXiv:1602.02830, Mar. 2016. [2]? M. Rastegari et al., arXiv:1603.05279, Aug. 2016. [3]? L. Hou et al., arXiv:1611.01600, Nov. 2016. [4]? F. Li et al., NIPS, 2016 (arXiv:1605.04711v2). [5]? I. Hubara et al., arXiv:1609.07061, Sep. 2016. [6]? H. Nakahara et al., FPGA, 2017, to be published. [7]? E. Nurvitadhi et al., FPT, 2016, pp. 77-84. [8]? H. Nakahara et al., FPT, 2016, pp. 273-276. [9]? Y-H. Chen et al., ISSCC, 2016, pp. 262-263. [10]?J. Sim et al., ISSCC, 2016, pp. 264-265. [11]?B. Moons et al., VLSI Circuits, 2016, pp. 178-179. Publisher Copyright: {\textcopyright} 2017 JSAP. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.; 31st Symposium on VLSI Circuits, VLSI Circuits 2017 ; Conference date: 05-06-2017 Through 08-06-2017",

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N2 - A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing architecture and stores varieties of binary/ternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip. The 0.6 W, 1.4 TOPS chip achieves performance and energy efficiency that is 10-102 and 102-104 times better than a CPU/GPU/FPGA.

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BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS

Abstract

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UN SDGs

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