BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS

Kota Ando; Kodai Ueyoshi; Kentaro Orimo; Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Tadahiro Kuroda; Masato Motomura

doi:10.23919/VLSIC.2017.8008533

BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda, Masato Motomura

Department of Electronics and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Citations (Scopus)

Abstract

A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing architecture and stores varieties of binary/ternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip. The 0.6 W, 1.4 TOPS chip achieves performance and energy efficiency that is 10-10² and 10²-10⁴ times better than a CPU/GPU/FPGA.

Original language	English
Title of host publication	2017 Symposium on VLSI Circuits, VLSI Circuits 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C24-C25
ISBN (Electronic)	9784863486065
DOIs	https://doi.org/10.23919/VLSIC.2017.8008533
Publication status	Published - 2017 Aug 10
Event	31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan Duration: 2017 Jun 5 → 2017 Jun 8

Other

Other	31st Symposium on VLSI Circuits, VLSI Circuits 2017
Country	Japan
City	Kyoto
Period	17/6/5 → 17/6/8

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ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Ando, K., Ueyoshi, K., Orimo, K., Yonekawa, H., Sato, S., Nakahara, H., ... Motomura, M. (2017). BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (pp. C24-C25). [8008533] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2017.8008533

BRein memory : A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS. / Ando, Kota; Ueyoshi, Kodai; Orimo, Kentaro; Yonekawa, Haruyoshi; Sato, Shimpei; Nakahara, Hiroki; Ikebe, Masayuki; Asai, Tetsuya; Takamaeda-Yamazaki, Shinya; Kuroda, Tadahiro; Motomura, Masato.

2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. C24-C25 8008533.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ando, K, Ueyoshi, K, Orimo, K, Yonekawa, H, Sato, S, Nakahara, H, Ikebe, M, Asai, T, Takamaeda-Yamazaki, S, Kuroda, T & Motomura, M 2017, BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS. in 2017 Symposium on VLSI Circuits, VLSI Circuits 2017., 8008533, Institute of Electrical and Electronics Engineers Inc., pp. C24-C25, 31st Symposium on VLSI Circuits, VLSI Circuits 2017, Kyoto, Japan, 17/6/5. https://doi.org/10.23919/VLSIC.2017.8008533

Ando K, Ueyoshi K, Orimo K, Yonekawa H, Sato S, Nakahara H et al. BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. C24-C25. 8008533 https://doi.org/10.23919/VLSIC.2017.8008533

Ando, Kota ; Ueyoshi, Kodai ; Orimo, Kentaro ; Yonekawa, Haruyoshi ; Sato, Shimpei ; Nakahara, Hiroki ; Ikebe, Masayuki ; Asai, Tetsuya ; Takamaeda-Yamazaki, Shinya ; Kuroda, Tadahiro ; Motomura, Masato. / BRein memory : A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS. 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. C24-C25

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Access to Document

10.23919/VLSIC.2017.8008533