BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda, Masato Motomura

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    30 Citations (Scopus)

    Abstract

    A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing architecture and stores varieties of binary/ternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip. The 0.6 W, 1.4 TOPS chip achieves performance and energy efficiency that is 10-102 and 102-104 times better than a CPU/GPU/FPGA.

    Original languageEnglish
    Title of host publication2017 Symposium on VLSI Circuits, VLSI Circuits 2017
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    PagesC24-C25
    ISBN (Electronic)9784863486065
    DOIs
    Publication statusPublished - 2017 Aug 10
    Event31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan
    Duration: 2017 Jun 52017 Jun 8

    Other

    Other31st Symposium on VLSI Circuits, VLSI Circuits 2017
    CountryJapan
    CityKyoto
    Period17/6/517/6/8

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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  • Cite this

    Ando, K., Ueyoshi, K., Orimo, K., Yonekawa, H., Sato, S., Nakahara, H., Ikebe, M., Asai, T., Takamaeda-Yamazaki, S., Kuroda, T., & Motomura, M. (2017). BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (pp. C24-C25). [8008533] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2017.8008533