TY - JOUR
T1 - BRein Memory
T2 - A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W
AU - Ando, Kota
AU - Ueyoshi, Kodai
AU - Orimo, Kentaro
AU - Yonekawa, Haruyoshi
AU - Sato, Shimpei
AU - Nakahara, Hiroki
AU - Takamaeda-Yamazaki, Shinya
AU - Ikebe, Masayuki
AU - Asai, Tetsuya
AU - Kuroda, Tadahiro
AU - Motomura, Masato
PY - 2017/12/19
Y1 - 2017/12/19
N2 - A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.
AB - A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.
KW - Binary neural networks
KW - Biological neural networks
KW - in-memory processing
KW - Memory management
KW - near-memory processing
KW - neural networks
KW - Neurons
KW - Parallel processing
KW - Random access memory
KW - reconfigurable array
KW - System-on-chip
KW - ternary neural networks
UR - http://www.scopus.com/inward/record.url?scp=85039791875&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85039791875&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2017.2778702
DO - 10.1109/JSSC.2017.2778702
M3 - Article
AN - SCOPUS:85039791875
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
ER -