BRein Memory

A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

Research output: Contribution to journal › Article

17 Citations (Scopus)

Abstract

A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.

Original languageEnglish
JournalIEEE Journal of Solid-State Circuits
DOIs
Publication statusAccepted/In press - 2017 Dec 19

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Particle accelerators
Neural networks
Data storage equipment
Energy efficiency
Clocks
Electric power utilization
Processing
Deep neural networks

Keywords

  • Binary neural networks
  • Biological neural networks
  • in-memory processing
  • Memory management
  • near-memory processing
  • neural networks
  • Neurons
  • Parallel processing
  • Random access memory
  • reconfigurable array
  • System-on-chip
  • ternary neural networks

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

BRein Memory : A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. / Ando, Kota; Ueyoshi, Kodai; Orimo, Kentaro; Yonekawa, Haruyoshi; Sato, Shimpei; Nakahara, Hiroki; Takamaeda-Yamazaki, Shinya; Ikebe, Masayuki; Asai, Tetsuya; Kuroda, Tadahiro; Motomura, Masato.

In: IEEE Journal of Solid-State Circuits, 19.12.2017.

Research output: Contribution to journal › Article

Ando, K, Ueyoshi, K, Orimo, K, Yonekawa, H, Sato, S, Nakahara, H, Takamaeda-Yamazaki, S, Ikebe, M, Asai, T, Kuroda, T & Motomura, M 2017, 'BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W', IEEE Journal of Solid-State Circuits. https://doi.org/10.1109/JSSC.2017.2778702
Ando K, Ueyoshi K, Orimo K, Yonekawa H, Sato S, Nakahara H et al. BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE Journal of Solid-State Circuits. 2017 Dec 19. https://doi.org/10.1109/JSSC.2017.2778702
Ando, Kota ; Ueyoshi, Kodai ; Orimo, Kentaro ; Yonekawa, Haruyoshi ; Sato, Shimpei ; Nakahara, Hiroki ; Takamaeda-Yamazaki, Shinya ; Ikebe, Masayuki ; Asai, Tetsuya ; Kuroda, Tadahiro ; Motomura, Masato. / BRein Memory : A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. In: IEEE Journal of Solid-State Circuits. 2017.
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