BRein Memory

A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

Research output: Contribution to journalArticle

17 Citations (Scopus)

Abstract

A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.

Original languageEnglish
JournalIEEE Journal of Solid-State Circuits
DOIs
Publication statusAccepted/In press - 2017 Dec 19

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Particle accelerators
Neural networks
Data storage equipment
Energy efficiency
Clocks
Electric power utilization
Processing
Deep neural networks

Keywords

  • Binary neural networks
  • Biological neural networks
  • in-memory processing
  • Memory management
  • near-memory processing
  • neural networks
  • Neurons
  • Parallel processing
  • Random access memory
  • reconfigurable array
  • System-on-chip
  • ternary neural networks

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

BRein Memory : A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. / Ando, Kota; Ueyoshi, Kodai; Orimo, Kentaro; Yonekawa, Haruyoshi; Sato, Shimpei; Nakahara, Hiroki; Takamaeda-Yamazaki, Shinya; Ikebe, Masayuki; Asai, Tetsuya; Kuroda, Tadahiro; Motomura, Masato.

In: IEEE Journal of Solid-State Circuits, 19.12.2017.

Research output: Contribution to journalArticle

Ando, Kota ; Ueyoshi, Kodai ; Orimo, Kentaro ; Yonekawa, Haruyoshi ; Sato, Shimpei ; Nakahara, Hiroki ; Takamaeda-Yamazaki, Shinya ; Ikebe, Masayuki ; Asai, Tetsuya ; Kuroda, Tadahiro ; Motomura, Masato. / BRein Memory : A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. In: IEEE Journal of Solid-State Circuits. 2017.
@article{9e5be92965704ef687d044d0d091a613,
title = "BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W",
abstract = "A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.",
keywords = "Binary neural networks, Biological neural networks, in-memory processing, Memory management, near-memory processing, neural networks, Neurons, Parallel processing, Random access memory, reconfigurable array, System-on-chip, ternary neural networks",
author = "Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura",
year = "2017",
month = "12",
day = "19",
doi = "10.1109/JSSC.2017.2778702",
language = "English",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - BRein Memory

T2 - A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

AU - Ando, Kota

AU - Ueyoshi, Kodai

AU - Orimo, Kentaro

AU - Yonekawa, Haruyoshi

AU - Sato, Shimpei

AU - Nakahara, Hiroki

AU - Takamaeda-Yamazaki, Shinya

AU - Ikebe, Masayuki

AU - Asai, Tetsuya

AU - Kuroda, Tadahiro

AU - Motomura, Masato

PY - 2017/12/19

Y1 - 2017/12/19

N2 - A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.

AB - A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.

KW - Binary neural networks

KW - Biological neural networks

KW - in-memory processing

KW - Memory management

KW - near-memory processing

KW - neural networks

KW - Neurons

KW - Parallel processing

KW - Random access memory

KW - reconfigurable array

KW - System-on-chip

KW - ternary neural networks

UR - http://www.scopus.com/inward/record.url?scp=85039791875&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85039791875&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2017.2778702

DO - 10.1109/JSSC.2017.2778702

M3 - Article

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

ER -