BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

    Research output: Contribution to journalArticlepeer-review

    51 Citations (Scopus)

    Abstract

    A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.

    Original languageEnglish
    Pages (from-to)983-994
    Number of pages12
    JournalIEEE Journal of Solid-State Circuits
    Volume53
    Issue number4
    DOIs
    Publication statusPublished - 2018 Apr

    Keywords

    • Binary neural networks
    • in-memory processing
    • near-memory processing
    • neural networks
    • reconfigurable array
    • ternary neural networks

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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