Cache coherency protocol for multiprocessor chip

Takuya Terasawa, Satoshi Ogura, Keisuke Inoue, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A snoop cache protocol is proposed for the WSI implementation which minimizes the access to the shared memory. In modified-Keio protocol, both write-invalidate and write-update type protocols can be used according to the nature of the shared data. It also supports the simple synchronization mechanism with Fetch&Dec operation and inter-processor interrupt. Detailed simulation with practical parallel applications demonstrates the efficiency of this proposed protocol.

Original languageEnglish
Title of host publicationProceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
EditorsStuart Tewkbury, Glenn Chapman
PublisherIEEE
Pages238-247
Number of pages10
Publication statusPublished - 1995
Externally publishedYes
EventProceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
Duration: 1995 Jan 181995 Jan 20

Other

OtherProceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration
CitySan Francisco, CA, USA
Period95/1/1895/1/20

Fingerprint

central processing units
synchronism
Synchronization
chips
Data storage equipment
simulation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Condensed Matter Physics

Cite this

Terasawa, T., Ogura, S., Inoue, K., & Amano, H. (1995). Cache coherency protocol for multiprocessor chip. In S. Tewkbury, & G. Chapman (Eds.), Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon (pp. 238-247). IEEE.

Cache coherency protocol for multiprocessor chip. / Terasawa, Takuya; Ogura, Satoshi; Inoue, Keisuke; Amano, Hideharu.

Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. ed. / Stuart Tewkbury; Glenn Chapman. IEEE, 1995. p. 238-247.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Terasawa, T, Ogura, S, Inoue, K & Amano, H 1995, Cache coherency protocol for multiprocessor chip. in S Tewkbury & G Chapman (eds), Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. IEEE, pp. 238-247, Proceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, CA, USA, 95/1/18.
Terasawa T, Ogura S, Inoue K, Amano H. Cache coherency protocol for multiprocessor chip. In Tewkbury S, Chapman G, editors, Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. IEEE. 1995. p. 238-247
Terasawa, Takuya ; Ogura, Satoshi ; Inoue, Keisuke ; Amano, Hideharu. / Cache coherency protocol for multiprocessor chip. Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. editor / Stuart Tewkbury ; Glenn Chapman. IEEE, 1995. pp. 238-247
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