Cache coherency protocol for multiprocessor chip

Takuya Terasawa, Satoshi Ogura, Keisuke Inoue, Hideharu Amano

Research output: Contribution to journalConference article

5 Citations (Scopus)

Abstract

A snoop cache protocol is proposed for the WSI implementation which minimizes the access to the shared memory. In modified-Keio protocol, both write-invalidate and write-update type protocols can be used according to the nature of the shared data. It also supports the simple synchronization mechanism with Fetch&Dec operation and inter-processor interrupt. Detailed simulation with practical parallel applications demonstrates the efficiency of this proposed protocol.

Original languageEnglish
Pages (from-to)238-247
Number of pages10
JournalProceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
Publication statusPublished - 1995 Jan 1
Externally publishedYes
EventProceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
Duration: 1995 Jan 181995 Jan 20

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Condensed Matter Physics

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