Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability

Tadahiro Kuroda; Tetsuya Fujita; Makato Noda; Yasushi Itabashi; Satohiko Kabumoto; T. S. Wong; Dave Beeson; Dave Gray

doi:10.1109/4.509868

Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability

Tadahiro Kuroda, Tetsuya Fujita, Makato Noda, Yasushi Itabashi, Satohiko Kabumoto, T. S. Wong, Dave Beeson, Dave Gray

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self-aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO = 1 and C_L = 0.55-pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied.

Original language	English
Pages (from-to)	819-827
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	31
Issue number	6
DOIs	https://doi.org/10.1109/4.509868
Publication status	Published - 1996 Jun
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.509868

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@article{2b44e5a1175d46b8afaa581d473f3ab9,

title = "Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability",

abstract = "This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self-aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO = 1 and CL = 0.55-pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied.",

author = "Tadahiro Kuroda and Tetsuya Fujita and Makato Noda and Yasushi Itabashi and Satohiko Kabumoto and Wong, {T. S.} and Dave Beeson and Dave Gray",

year = "1996",

month = jun,

doi = "10.1109/4.509868",

language = "English",

volume = "31",

pages = "819--827",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability

AU - Kuroda, Tadahiro

AU - Fujita, Tetsuya

AU - Noda, Makato

AU - Itabashi, Yasushi

AU - Kabumoto, Satohiko

AU - Wong, T. S.

AU - Beeson, Dave

AU - Gray, Dave

PY - 1996/6

Y1 - 1996/6

N2 - This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self-aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO = 1 and CL = 0.55-pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied.

AB - This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self-aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO = 1 and CL = 0.55-pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied.

UR - http://www.scopus.com/inward/record.url?scp=0030172242&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030172242&partnerID=8YFLogxK

U2 - 10.1109/4.509868

DO - 10.1109/4.509868

M3 - Article

AN - SCOPUS:0030172242

SN - 0018-9200

VL - 31

SP - 819

EP - 827

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 6

ER -

Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability

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