Carrier transport and stress engineering in advanced nanoscale MOS transistors

Ken Uchida, Masumi Saitoh

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    This paper reviews the carrier transport mechanisms and stress engineering in advanced nanoscale MOSFETs. First, carrier transport in bulk (100) and (110) MOSFETs is reviewed. Subband structure engineering to enhance mobility as well as ballistic current is also examined.

    Original languageEnglish
    Title of host publication2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09
    Pages6-7
    Number of pages2
    DOIs
    Publication statusPublished - 2009 Dec 1
    Event2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09 - Hsinchu, Taiwan, Province of China
    Duration: 2009 Apr 272009 Apr 29

    Publication series

    NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings

    Other

    Other2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09
    CountryTaiwan, Province of China
    CityHsinchu
    Period09/4/2709/4/29

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering

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  • Cite this

    Uchida, K., & Saitoh, M. (2009). Carrier transport and stress engineering in advanced nanoscale MOS transistors. In 2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09 (pp. 6-7). [5159267] (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VTSA.2009.5159267