Challenge and prospects for silicon SET/FET hybrid circuits

A. Toriumi, K. Uchida, R. Ohba, J. Koga

Research output: Contribution to journalConference article

6 Citations (Scopus)


Si SET devices are discussed from the viewpoint of suitability for CMOS technology. Since there are limitations in the application of devices with a low driving performance and no gain in the conventional circuit scheme, it is a challenge to implement their advantages into a chip for better performance as a total system. We propose a quantum function-embedded CMOS structure that should be open for the implementation of new devices. A key point is a graceful assimilation, since a sudden change in the architecture is not a solution at present. Although Si device/process technology will certainly be developed further, continuing investigation of the SET technology is necessary, if the CMOS technology is to extend into the 21st century, down to the sub-50 nm level.

Original languageEnglish
Pages (from-to)522-526
Number of pages5
JournalPhysica B: Condensed Matter
Issue number1-4
Publication statusPublished - 1999 Dec 1
EventProceedings of the 1999 11th International Conference on Nonequilibrium Carrier Dynamics in Semiconductors (HCIS-11) - Kyoto, Jpn
Duration: 1999 Jul 191999 Jul 23


ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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