A 44GB/s inductive-coupling DRAM/SoC interface is developed by PoP integration. It utilizes the advantages of both TSV and LPDDR by using a ThruChip Interface (TCI) and an ultra-thin fan-out wafer level package (UT-FOWLP). The TCI allows data communication between the stacked chips while the UT-FOWLP thins the chips stacking distance and provides the chips with power. This proposed DRAM/SoC interface outperforms WIO2 with TSV in terms of area efficiency (4× better), immunity from simultaneous switching output (SSO) noise (32× better) and manufacturing cost (40% cheaper). In addition, it outperforms LPDDR4 in PoP in terms of power dissipation (5× lower) and timing control easiness. The inductive-coupling interface is newly designed to allow 12× improvement on its area efficiency. By using overlapping coils with quadrature phase division multiplexing (PDM), the coil density is increased by 4 times. The coil density is further increased by 3 times by shortening communication distance with the UT-FOWLP.