Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs

Masao Suzuki, Naoaki Yamanaka, Michihiro Hirata, Shiro Kikuchi

Research output: Contribution to conferencePaper

4 Citations (Scopus)


An Si bipolar circuit technology for gigabit-per-second crosspoint switch LSIs is described. A novel circuit design and a super-self-aligned process technology were adopted, and 8 × 8 and 16 × 16 (+16) crosspoint switch LSIs were fabricated. The LSIs successfully switched with a bit error rate of less than 10-9 at 2.5 Gb/s using a 29-1 pseudorandom NRZ sequence. Pulse jitters are made less than 76 ps at 2 Gb/s by utilizing a small internal voltage swing (225 mV) with a differential CML. The LSIs have full emitter-coupled logic (ECL)-compatible interfaces, -4/-2-V power supply voltages, and a power consumption of less than 0.9 W for an 8 × 8 LSI, and 2.8 W for a 16 × 16 (+16) LSI. These results confirm that the proposed technologies are applicable to future B-ISDN (broadband integrated services digital network) communication systems.

Original languageEnglish
Number of pages2
Publication statusPublished - 1989 Dec 1
Externally publishedYes
EventSymposium on VLSI Circuits 1989 - Kyoto, Japan
Duration: 1989 May 251989 May 27


OtherSymposium on VLSI Circuits 1989
CityKyoto, Japan

ASJC Scopus subject areas

  • Engineering(all)

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    Suzuki, M., Yamanaka, N., Hirata, M., & Kikuchi, S. (1989). Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs. 65-66. Paper presented at Symposium on VLSI Circuits 1989, Kyoto, Japan, .