Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs

Masao Suzuki, Naoaki Yamanaka, Michihiro Hirata, Shiro Kikuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

An Si bipolar circuit technology for gigabit-per-second crosspoint switch LSIs is described. A novel circuit design and a super-self-aligned process technology were adopted, and 8 × 8 and 16 × 16 (+16) crosspoint switch LSIs were fabricated. The LSIs successfully switched with a bit error rate of less than 10-9 at 2.5 Gb/s using a 29-1 pseudorandom NRZ sequence. Pulse jitters are made less than 76 ps at 2 Gb/s by utilizing a small internal voltage swing (225 mV) with a differential CML. The LSIs have full emitter-coupled logic (ECL)-compatible interfaces, -4/-2-V power supply voltages, and a power consumption of less than 0.9 W for an 8 × 8 LSI, and 2.8 W for a 16 × 16 (+16) LSI. These results confirm that the proposed technologies are applicable to future B-ISDN (broadband integrated services digital network) communication systems.

Original languageEnglish
Title of host publicationSymp VLSI Circuit 1989
Editors Anon
PublisherPubl by IEEE
Pages65-66
Number of pages2
Publication statusPublished - 1989
Externally publishedYes
EventSymposium on VLSI Circuits 1989 - Kyoto, Japan
Duration: 1989 May 251989 May 27

Other

OtherSymposium on VLSI Circuits 1989
CityKyoto, Japan
Period89/5/2589/5/27

Fingerprint

Switches
Networks (circuits)
Emitter coupled logic circuits
Voice/data communication systems
Electric potential
Jitter
Bit error rate
Communication systems
Electric power utilization

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Suzuki, M., Yamanaka, N., Hirata, M., & Kikuchi, S. (1989). Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs. In Anon (Ed.), Symp VLSI Circuit 1989 (pp. 65-66). Publ by IEEE.

Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs. / Suzuki, Masao; Yamanaka, Naoaki; Hirata, Michihiro; Kikuchi, Shiro.

Symp VLSI Circuit 1989. ed. / Anon. Publ by IEEE, 1989. p. 65-66.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Suzuki, M, Yamanaka, N, Hirata, M & Kikuchi, S 1989, Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs. in Anon (ed.), Symp VLSI Circuit 1989. Publ by IEEE, pp. 65-66, Symposium on VLSI Circuits 1989, Kyoto, Japan, 89/5/25.
Suzuki M, Yamanaka N, Hirata M, Kikuchi S. Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs. In Anon, editor, Symp VLSI Circuit 1989. Publ by IEEE. 1989. p. 65-66
Suzuki, Masao ; Yamanaka, Naoaki ; Hirata, Michihiro ; Kikuchi, Shiro. / Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs. Symp VLSI Circuit 1989. editor / Anon. Publ by IEEE, 1989. pp. 65-66
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