CLAHE implementation and evaluation on a low-end FPGA board by high-level synthesis

Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano

Research output: Contribution to journalArticlepeer-review

Abstract

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing to improve the quality of the image. Contrast Limited Adaptive Histogram Equalization (CLAHE) is one of such techniques to improve the quality of the image for the side mirror camera, which requires a large computation performance. Here, an implementation method of CLAHE on a low-end FPGA board by high-level synthesis is proposed. CLAHE has two main processing parts: cumulative distribution function (CDF) generation, and bilinear interpolation. During the CDF generation, the effect of increasing loop initiation interval can be greatly reduced by placing multiple Processing Elements (PEs). and during the interpolation, latency and BRAM usage were reduced by revising how to hold CDF and calculation method. Finally, by connecting each module with streaming interfaces, using data flow pragmas, overlapping processing, and hiding data transfer, our HLS implementation achieved a comparable result to that of HDL. We parameterized the components of the algorithm so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga clahe.

Original languageEnglish
Pages (from-to)2048-2056
Number of pages9
JournalIEICE Transactions on Information and Systems
VolumeE104D
Issue number12
DOIs
Publication statusPublished - 2021

Keywords

  • CLAHE
  • FPGA
  • High-level synthesis
  • Image processing
  • Side camera mirror

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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