CLAHE implementation on a low-end FPGA board by high-level synthesis

Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing for improving quality. This paper describes a design of Contrast Limited Adaptive Histogram Equalization (CLAHE), which improves the quality of the dark image for the side mirror camera, on a low-end FPGA board by high-level synthesis. By constituting CLAHE as a data flow design flow, we could achieve performance comparable to the implementation with HDL. The code is parameterized so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga_clahe.

Original languageEnglish
Title of host publicationProceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages282-285
Number of pages4
ISBN (Electronic)9781728199191
DOIs
Publication statusPublished - 2020 Nov
Event8th International Symposium on Computing and Networking Workshops, CANDARW 2020 - Virtual, Naha, Japan
Duration: 2020 Nov 242020 Nov 27

Publication series

NameProceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020

Conference

Conference8th International Symposium on Computing and Networking Workshops, CANDARW 2020
CountryJapan
CityVirtual, Naha
Period20/11/2420/11/27

Keywords

  • clahe
  • FPGA
  • image processing
  • side camera mirror

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Hardware and Architecture
  • Computational Mathematics
  • Control and Optimization

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