CMOS design challenges to power wall

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Citations (Scopus)

Abstract

CMOS power dissipation has been increasing due to the increase in power density. The power dissipation increased fourfold every three years until the early 1990's, due to a constant voltage scaling. Recently, a constant field scaling has been applied to reduce power dissipation, where the power density is increased proportional to the 0.7th power of scaling factor, resulting in power increase by twice every 6.5 years. It is considered that the power dissipation of CMOS chips will steadily be increased as a natural result of device scaling. Technology scaling will become difficult due to the power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

Original languageEnglish
Title of host publication2001 International Microprocesses and Nanotechnology Conference, MNC 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages6-7
Number of pages2
ISBN (Print)4891140178, 9784891140175
DOIs
Publication statusPublished - 2001
EventInternational Microprocesses and Nanotechnology Conference, MNC 2001 - Shimane, Japan
Duration: 2001 Oct 312001 Nov 2

Other

OtherInternational Microprocesses and Nanotechnology Conference, MNC 2001
CountryJapan
CityShimane
Period01/10/3101/11/2

Fingerprint

Energy dissipation
CMOS
dissipation
Technology
scaling
Equipment and Supplies
radiant flux density
horizon
communication
chips
Communication
electric potential
energy

ASJC Scopus subject areas

  • Biotechnology
  • Fluid Flow and Transfer Processes
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

Cite this

Kuroda, T. (2001). CMOS design challenges to power wall. In 2001 International Microprocesses and Nanotechnology Conference, MNC 2001 (pp. 6-7). [984030] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IMNC.2001.984030

CMOS design challenges to power wall. / Kuroda, Tadahiro.

2001 International Microprocesses and Nanotechnology Conference, MNC 2001. Institute of Electrical and Electronics Engineers Inc., 2001. p. 6-7 984030.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kuroda, T 2001, CMOS design challenges to power wall. in 2001 International Microprocesses and Nanotechnology Conference, MNC 2001., 984030, Institute of Electrical and Electronics Engineers Inc., pp. 6-7, International Microprocesses and Nanotechnology Conference, MNC 2001, Shimane, Japan, 01/10/31. https://doi.org/10.1109/IMNC.2001.984030
Kuroda T. CMOS design challenges to power wall. In 2001 International Microprocesses and Nanotechnology Conference, MNC 2001. Institute of Electrical and Electronics Engineers Inc. 2001. p. 6-7. 984030 https://doi.org/10.1109/IMNC.2001.984030
Kuroda, Tadahiro. / CMOS design challenges to power wall. 2001 International Microprocesses and Nanotechnology Conference, MNC 2001. Institute of Electrical and Electronics Engineers Inc., 2001. pp. 6-7
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