### Abstract

A McCulloch-Pitts neuron is the simplified neuron model which has been successfully used for many optimisation problems. The neural network with the hysteresis property can suppress the oscillatory behaviours of neural dynamics so that the convergence time is shortened. In this paper, digital CMOS layout design of the hysteresis McCulloch-Pitts neuron is presented. Based on simulation results using the hysteresis McCulloch-Pitts binary neuron model, a 6-bit fixed point 2's complement arithmetic was adopted for the calculation of the input U of each neuron. Each neuron needs 204 transistors and requires a 399 λ × 368 λ layout area using the MOSIS scalable CMOS/bulk (SCMOS) VLSI technology with 2 μm rule of P well, double level metal. Layout design of the hysteresis McCulloch-Pitts neuron chip was completed, and fabrication of the chip and the design for the test circuit for the fabricated CMOS VLSI chip are underway at present.

Original language | English |
---|---|

Pages (from-to) | 2093-2095 |

Number of pages | 3 |

Journal | Electronics Letters |

Volume | 26 |

Issue number | 25 |

Publication status | Published - 1990 Dec 6 |

Externally published | Yes |

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### ASJC Scopus subject areas

- Electrical and Electronic Engineering

### Cite this

*Electronics Letters*,

*26*(25), 2093-2095.

**CMOS layout design of the hysteresis McCulloch-Pitts neuron.** / Kurokawa, T.; Lee, K. C.; Cho, Y. B.; Takefuji, Yoshiyasu.

Research output: Contribution to journal › Article

*Electronics Letters*, vol. 26, no. 25, pp. 2093-2095.

}

TY - JOUR

T1 - CMOS layout design of the hysteresis McCulloch-Pitts neuron

AU - Kurokawa, T.

AU - Lee, K. C.

AU - Cho, Y. B.

AU - Takefuji, Yoshiyasu

PY - 1990/12/6

Y1 - 1990/12/6

N2 - A McCulloch-Pitts neuron is the simplified neuron model which has been successfully used for many optimisation problems. The neural network with the hysteresis property can suppress the oscillatory behaviours of neural dynamics so that the convergence time is shortened. In this paper, digital CMOS layout design of the hysteresis McCulloch-Pitts neuron is presented. Based on simulation results using the hysteresis McCulloch-Pitts binary neuron model, a 6-bit fixed point 2's complement arithmetic was adopted for the calculation of the input U of each neuron. Each neuron needs 204 transistors and requires a 399 λ × 368 λ layout area using the MOSIS scalable CMOS/bulk (SCMOS) VLSI technology with 2 μm rule of P well, double level metal. Layout design of the hysteresis McCulloch-Pitts neuron chip was completed, and fabrication of the chip and the design for the test circuit for the fabricated CMOS VLSI chip are underway at present.

AB - A McCulloch-Pitts neuron is the simplified neuron model which has been successfully used for many optimisation problems. The neural network with the hysteresis property can suppress the oscillatory behaviours of neural dynamics so that the convergence time is shortened. In this paper, digital CMOS layout design of the hysteresis McCulloch-Pitts neuron is presented. Based on simulation results using the hysteresis McCulloch-Pitts binary neuron model, a 6-bit fixed point 2's complement arithmetic was adopted for the calculation of the input U of each neuron. Each neuron needs 204 transistors and requires a 399 λ × 368 λ layout area using the MOSIS scalable CMOS/bulk (SCMOS) VLSI technology with 2 μm rule of P well, double level metal. Layout design of the hysteresis McCulloch-Pitts neuron chip was completed, and fabrication of the chip and the design for the test circuit for the fabricated CMOS VLSI chip are underway at present.

UR - http://www.scopus.com/inward/record.url?scp=0025701942&partnerID=8YFLogxK

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M3 - Article

VL - 26

SP - 2093

EP - 2095

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 25

ER -