Code compression with split echo instructions

Iver Stubdal; Arda Karaduman; Hideharu Amano

doi:10.1587/transinf.E92.D.1650

Code compression with split echo instructions

Iver Stubdal, Arda Karaduman, Hideharu Amano

Department of Information and Computer Science

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Code density is often a critical issue in embedded computers, since the memory size of embedded systems is strictly limited. Echo instructions have been proposed as a method for reducing code size. This paper presents a new type of echo instruction, split echo, and evaluates an implementation of both split echo and traditional echo instructions on a MIPS R3000 based processor. Evaluation results show that memory requirement is reduced by 12% on average with small additional hardware cost.

Original language	English
Pages (from-to)	1650-1656
Number of pages	7
Journal	IEICE Transactions on Information and Systems
Volume	E92-D
Issue number	9
DOIs	https://doi.org/10.1587/transinf.E92.D.1650
Publication status	Published - 2009

Keywords

Code size
Compression
Echo instructions
MIPS processor

ASJC Scopus subject areas

Software
Hardware and Architecture
Computer Vision and Pattern Recognition
Electrical and Electronic Engineering
Artificial Intelligence

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10.1587/transinf.E92.D.1650

Cite this

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AB - Code density is often a critical issue in embedded computers, since the memory size of embedded systems is strictly limited. Echo instructions have been proposed as a method for reducing code size. This paper presents a new type of echo instruction, split echo, and evaluates an implementation of both split echo and traditional echo instructions on a MIPS R3000 based processor. Evaluation results show that memory requirement is reduced by 12% on average with small additional hardware cost.

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Code compression with split echo instructions

Abstract

Keywords

ASJC Scopus subject areas

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