Compact outside-rail circuit structure by single-cascode two-transistor topology

A. Tamtrakarn, Hiroki Ishikuro, K. Ishida, T. Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a new compact outside-rail circuit structure for future scaled CMOS technology. The proposed circuit is composed of only two transistors connected into a single cascode style for increasing supply voltage to one more nominal supply voltage (VDD). The circuit is manufactured and measured. Reliability is also verified by the trajectory plot for gate-source voltage and gate-drain voltage of all devices. The results confirm that triple of nominal supply voltage can be used without any overstress in all CMOS devices. The proposed circuit saves 52% area and improves speed for 40% of the conventional approach in the case of 4VDD. An example of outside-rail opamp is also proposed by using the proposed circuit.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
Pages619-622
Number of pages4
DOIs
Publication statusPublished - 2006
EventIEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States
Duration: 2006 Sep 102006 Sep 13

Other

OtherIEEE 2006 Custom Integrated Circuits Conference, CICC 2006
CountryUnited States
CitySan Jose, CA
Period06/9/1006/9/13

Fingerprint

Rails
Transistors
Topology
Networks (circuits)
Electric potential
Operational amplifiers
Trajectories

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Tamtrakarn, A., Ishikuro, H., Ishida, K., & Sakurai, T. (2006). Compact outside-rail circuit structure by single-cascode two-transistor topology. In Proceedings of the Custom Integrated Circuits Conference (pp. 619-622). [4115035] https://doi.org/10.1109/CICC.2006.320836

Compact outside-rail circuit structure by single-cascode two-transistor topology. / Tamtrakarn, A.; Ishikuro, Hiroki; Ishida, K.; Sakurai, T.

Proceedings of the Custom Integrated Circuits Conference. 2006. p. 619-622 4115035.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tamtrakarn, A, Ishikuro, H, Ishida, K & Sakurai, T 2006, Compact outside-rail circuit structure by single-cascode two-transistor topology. in Proceedings of the Custom Integrated Circuits Conference., 4115035, pp. 619-622, IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, San Jose, CA, United States, 06/9/10. https://doi.org/10.1109/CICC.2006.320836
Tamtrakarn A, Ishikuro H, Ishida K, Sakurai T. Compact outside-rail circuit structure by single-cascode two-transistor topology. In Proceedings of the Custom Integrated Circuits Conference. 2006. p. 619-622. 4115035 https://doi.org/10.1109/CICC.2006.320836
Tamtrakarn, A. ; Ishikuro, Hiroki ; Ishida, K. ; Sakurai, T. / Compact outside-rail circuit structure by single-cascode two-transistor topology. Proceedings of the Custom Integrated Circuits Conference. 2006. pp. 619-622
@inproceedings{96fdae0180ab4a9c951e82fbf6310695,
title = "Compact outside-rail circuit structure by single-cascode two-transistor topology",
abstract = "This paper presents a new compact outside-rail circuit structure for future scaled CMOS technology. The proposed circuit is composed of only two transistors connected into a single cascode style for increasing supply voltage to one more nominal supply voltage (VDD). The circuit is manufactured and measured. Reliability is also verified by the trajectory plot for gate-source voltage and gate-drain voltage of all devices. The results confirm that triple of nominal supply voltage can be used without any overstress in all CMOS devices. The proposed circuit saves 52{\%} area and improves speed for 40{\%} of the conventional approach in the case of 4VDD. An example of outside-rail opamp is also proposed by using the proposed circuit.",
author = "A. Tamtrakarn and Hiroki Ishikuro and K. Ishida and T. Sakurai",
year = "2006",
doi = "10.1109/CICC.2006.320836",
language = "English",
isbn = "1424400767",
pages = "619--622",
booktitle = "Proceedings of the Custom Integrated Circuits Conference",

}

TY - GEN

T1 - Compact outside-rail circuit structure by single-cascode two-transistor topology

AU - Tamtrakarn, A.

AU - Ishikuro, Hiroki

AU - Ishida, K.

AU - Sakurai, T.

PY - 2006

Y1 - 2006

N2 - This paper presents a new compact outside-rail circuit structure for future scaled CMOS technology. The proposed circuit is composed of only two transistors connected into a single cascode style for increasing supply voltage to one more nominal supply voltage (VDD). The circuit is manufactured and measured. Reliability is also verified by the trajectory plot for gate-source voltage and gate-drain voltage of all devices. The results confirm that triple of nominal supply voltage can be used without any overstress in all CMOS devices. The proposed circuit saves 52% area and improves speed for 40% of the conventional approach in the case of 4VDD. An example of outside-rail opamp is also proposed by using the proposed circuit.

AB - This paper presents a new compact outside-rail circuit structure for future scaled CMOS technology. The proposed circuit is composed of only two transistors connected into a single cascode style for increasing supply voltage to one more nominal supply voltage (VDD). The circuit is manufactured and measured. Reliability is also verified by the trajectory plot for gate-source voltage and gate-drain voltage of all devices. The results confirm that triple of nominal supply voltage can be used without any overstress in all CMOS devices. The proposed circuit saves 52% area and improves speed for 40% of the conventional approach in the case of 4VDD. An example of outside-rail opamp is also proposed by using the proposed circuit.

UR - http://www.scopus.com/inward/record.url?scp=39049171118&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=39049171118&partnerID=8YFLogxK

U2 - 10.1109/CICC.2006.320836

DO - 10.1109/CICC.2006.320836

M3 - Conference contribution

SN - 1424400767

SN - 9781424400768

SP - 619

EP - 622

BT - Proceedings of the Custom Integrated Circuits Conference

ER -