Compact outside-rail circuit structure by single-cascode two-transistor topology

A. Tamtrakarn; H. Ishikuro; K. Ishida; T. Sakurai

doi:10.1109/CICC.2006.320836

Compact outside-rail circuit structure by single-cascode two-transistor topology

A. Tamtrakarn, H. Ishikuro, K. Ishida, T. Sakurai

Department of Electronics and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a new compact outside-rail circuit structure for future scaled CMOS technology. The proposed circuit is composed of only two transistors connected into a single cascode style for increasing supply voltage to one more nominal supply voltage (V_DD). The circuit is manufactured and measured. Reliability is also verified by the trajectory plot for gate-source voltage and gate-drain voltage of all devices. The results confirm that triple of nominal supply voltage can be used without any overstress in all CMOS devices. The proposed circuit saves 52% area and improves speed for 40% of the conventional approach in the case of 4V_DD. An example of outside-rail opamp is also proposed by using the proposed circuit.

Original language	English
Title of host publication	Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Pages	619-622
Number of pages	4
DOIs	https://doi.org/10.1109/CICC.2006.320836
Publication status	Published - 2006
Event	IEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States Duration: 2006 Sept 10 → 2006 Sept 13

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Country/Territory	United States
City	San Jose, CA
Period	06/9/10 → 06/9/13

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2006.320836

Cite this

Compact outside-rail circuit structure by single-cascode two-transistor topology. / Tamtrakarn, A.; Ishikuro, H.; Ishida, K. et al.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006. 2006. p. 619-622 4115035 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tamtrakarn, A, Ishikuro, H, Ishida, K & Sakurai, T 2006, Compact outside-rail circuit structure by single-cascode two-transistor topology. in Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006., 4115035, Proceedings of the Custom Integrated Circuits Conference, pp. 619-622, IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, San Jose, CA, United States, 06/9/10. https://doi.org/10.1109/CICC.2006.320836

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title = "Compact outside-rail circuit structure by single-cascode two-transistor topology",

abstract = "This paper presents a new compact outside-rail circuit structure for future scaled CMOS technology. The proposed circuit is composed of only two transistors connected into a single cascode style for increasing supply voltage to one more nominal supply voltage (VDD). The circuit is manufactured and measured. Reliability is also verified by the trajectory plot for gate-source voltage and gate-drain voltage of all devices. The results confirm that triple of nominal supply voltage can be used without any overstress in all CMOS devices. The proposed circuit saves 52% area and improves speed for 40% of the conventional approach in the case of 4VDD. An example of outside-rail opamp is also proposed by using the proposed circuit.",

author = "A. Tamtrakarn and H. Ishikuro and K. Ishida and T. Sakurai",

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doi = "10.1109/CICC.2006.320836",

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series = "Proceedings of the Custom Integrated Circuits Conference",

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AU - Tamtrakarn, A.

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AB - This paper presents a new compact outside-rail circuit structure for future scaled CMOS technology. The proposed circuit is composed of only two transistors connected into a single cascode style for increasing supply voltage to one more nominal supply voltage (VDD). The circuit is manufactured and measured. Reliability is also verified by the trajectory plot for gate-source voltage and gate-drain voltage of all devices. The results confirm that triple of nominal supply voltage can be used without any overstress in all CMOS devices. The proposed circuit saves 52% area and improves speed for 40% of the conventional approach in the case of 4VDD. An example of outside-rail opamp is also proposed by using the proposed circuit.

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Compact outside-rail circuit structure by single-cascode two-transistor topology

Abstract

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