Compact outside-rail circuit structure by single-cascode two-transistor topology

A. Tamtrakarn, H. Ishikuro, K. Ishida, T. Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a new compact outside-rail circuit structure for future scaled CMOS technology. The proposed circuit is composed of only two transistors connected into a single cascode style for increasing supply voltage to one more nominal supply voltage (VDD). The circuit is manufactured and measured. Reliability is also verified by the trajectory plot for gate-source voltage and gate-drain voltage of all devices. The results confirm that triple of nominal supply voltage can be used without any overstress in all CMOS devices. The proposed circuit saves 52% area and improves speed for 40% of the conventional approach in the case of 4VDD. An example of outside-rail opamp is also proposed by using the proposed circuit.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Pages619-622
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
EventIEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States
Duration: 2006 Sep 102006 Sep 13

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

OtherIEEE 2006 Custom Integrated Circuits Conference, CICC 2006
CountryUnited States
CitySan Jose, CA
Period06/9/1006/9/13

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Tamtrakarn, A., Ishikuro, H., Ishida, K., & Sakurai, T. (2006). Compact outside-rail circuit structure by single-cascode two-transistor topology. In Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006 (pp. 619-622). [4115035] (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2006.320836