Comparative performance analysis of dual-rail domino logic and CMOS logic under near-threshold operation

Tsuyoshi Maruyama, Mototsugu Hamada, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The designs of an asynchronous dual-rail domino logic (DRDL) and the conventional CMOS logic under near-threshold operation are compared. The delay time and energy consumption of an 8-bit full adder pipeline are simulated using HSPICE with 180-nm CMOS technology. The results show that, considering process variations, DRDL is faster than CMOS below 1.1 V. The delay performance of DRDL at 0.25 V is equivalent to that of CMOS at 0.4 V, while the energy-delay product of DRDL is 40% smaller than that of CMOS.

Original languageEnglish
Title of host publication2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages25-28
Number of pages4
ISBN (Electronic)9781538673928
DOIs
Publication statusPublished - 2019 Jan 22
Event61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada
Duration: 2018 Aug 52018 Aug 8

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2018-August
ISSN (Print)1548-3746

Conference

Conference61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
CountryCanada
CityWindsor
Period18/8/518/8/8

Fingerprint

Rails
Adders
Time delay
Energy utilization
Pipelines

Keywords

  • Asynchronous circuit
  • Dual-rail domino logic
  • Energy-delay product
  • Full adder

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Maruyama, T., Hamada, M., & Kuroda, T. (2019). Comparative performance analysis of dual-rail domino logic and CMOS logic under near-threshold operation. In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018 (pp. 25-28). [8624078] (Midwest Symposium on Circuits and Systems; Vol. 2018-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2018.8624078

Comparative performance analysis of dual-rail domino logic and CMOS logic under near-threshold operation. / Maruyama, Tsuyoshi; Hamada, Mototsugu; Kuroda, Tadahiro.

2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 25-28 8624078 (Midwest Symposium on Circuits and Systems; Vol. 2018-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Maruyama, T, Hamada, M & Kuroda, T 2019, Comparative performance analysis of dual-rail domino logic and CMOS logic under near-threshold operation. in 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018., 8624078, Midwest Symposium on Circuits and Systems, vol. 2018-August, Institute of Electrical and Electronics Engineers Inc., pp. 25-28, 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, Canada, 18/8/5. https://doi.org/10.1109/MWSCAS.2018.8624078
Maruyama T, Hamada M, Kuroda T. Comparative performance analysis of dual-rail domino logic and CMOS logic under near-threshold operation. In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 25-28. 8624078. (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2018.8624078
Maruyama, Tsuyoshi ; Hamada, Mototsugu ; Kuroda, Tadahiro. / Comparative performance analysis of dual-rail domino logic and CMOS logic under near-threshold operation. 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 25-28 (Midwest Symposium on Circuits and Systems).
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