Self-heating effects (SHEs) of bulk and SOI FETs including 6-nm ultra-thin (UT) BOX devices are systematically investigated and compared using the four-terminal gate resistance technique. For bulk FETs, it has been verified for the first time that the SHE is not negligible in nanoscale devices mainly owing to a decrease in the thermal conductivity of the more heavily doped well. Furthermore, it has been demonstrated that the magnitude of the SHE strongly depends on the chip (ambient) temperature (Tchip). For SOI FETs, the impacts of BOX/SOI thinning are evaluated and explained in terms of the thermal conductivities of materials within heat dissipation paths. It has been demonstrated that the device temperature of 6-nm UT BOX SOI FETs is close to that of bulk FETs at Tchip under operating conditions. A thermal-aware device design of the UT Body and BOX (UTBB) structure is proposed on the basis of the evaluated BOX/SOI thickness dependences of the SHE. The SHE of UTBB FETs with a raised source/drain and/or shorter contact pitch could be comparable to that of bulk FETs in deeply scaled nodes. In addition, the doping concentration under the BOX should be optimized in order to achieve low and Tchip-independent SHE.